"Optimum" values of DDR3 slave ratio does not work

PA Nilsson

I have a board with a DDR layout almost identical to BeagleBoneBlack.

The board seems to run fine with the default BBB DDR3 settings, but when trying to tune the values I get odd "optimum" values from the tool.

I have followed the instructions here:

http://processors.wiki.ti.com/index.php/Sitara_Linux_Training:_Tuning_the_DDR3_Timings_on_BeagleBoneBlack

using the specified BBB gel file.

Inputs to the seed tool are:

PHY_INVERT_CLKOUT 0

Seed values used in CCS code
DATAx_PHY_RD DQS_SLAVE_RATIO   40
DATAx_PHY_FIFO_WE_SLAVE_RATIO   75
DATAx_PHY_WR DQS_SLAVE_RATIO   2

Register value
CMDx_PHY_CTRL_SLAVE_RATIO   80

Running the tool to tune the settings ends up with the following:

***************************************************************
   The Slave Ratio Search Program Values are...
***************************************************************
PARAMETER                       MAX | MIN | OPTIMUM | RANGE
***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO    0x3ff | 0x0bb | 0x25d | 0x344
DATA_PHY_FIFO_WE_SLAVE_RATIO   0x3ff | 0x000 | 0x1ff | 0x3ff
DATA_PHY_WR_DQS_SLAVE_RATIO    0x07a | 0x000 | 0x03d | 0x07a
DATA_PHY_WR_DATA_SLAVE_RATIO   0x3ff | 0x03c | 0x21d | 0x3c3
***************************************************************

===== END OF TEST =====

When using these values, u-boot then fails to start.

Any idea on why these values are so different from what a BBB generates?

I am running CCS Version: 6.1.0.00104

over 10 years ago

0 Lev Urusov over 10 years ago

Prodigy 140 points

It's almost like in my case: e2e.ti.com/.../439868
Which DDR3 chip you are using?

0 Biser Gatchev-XID over 10 years ago

TI__Guru**** 393215 points

Hi,

Can you post your Ratio Seed Excel sheet?

0 PA Nilsson over 10 years ago in reply to Lev Urusov

Prodigy 200 points

Same as BBB, Micron MT41K256M16HA-125E

0 PA Nilsson over 10 years ago in reply to Biser Gatchev-XID

Prodigy 200 points

If I knew how to post a file here I would...

But I have used this file:
processors.wiki.ti.com/.../RatioSeed_AM335x_boards.zip

With this input:
DDR clock frequency 400 MHz
PHY_INVERT_CLKOUT 0

Trace Length (inches)
Byte 0 Byte 1
DDR_CK trace 1.088 1.088
DDR_DQSx trace 0.941 0.9175

Intermediate values (per byte lane)
WR DQS 2 3
RD DQS 40 40
RD DQS GATE 76 75

Seed values used in CCS code
DATAx_PHY_RD DQS_SLAVE_RATIO 40
DATAx_PHY_FIFO_WE_SLAVE_RATIO 75
DATAx_PHY_WR DQS_SLAVE_RATIO 2

Register value
CMDx_PHY_CTRL_SLAVE_RATIO 80

/PA

0 PA Nilsson over 10 years ago in reply to Lev Urusov

Prodigy 200 points

@Lev, yes it looks very much the same.

0 Biser Gatchev-XID over 10 years ago in reply to PA Nilsson

TI__Guru**** 393215 points

Everything seems correct here. I will ask the DDR experts to look at this.

Aside from this, posting a file is easy - just drag and drop it in your reply window.

0 Lev Urusov over 10 years ago

Prodigy 140 points

Did you try the EDMA test (Scripts->AM335x DDR Tests->EDMA)? In my case the test discovered errors at some addresses, manual data editing confirmed erroneous operation of these cells.

0 PA Nilsson over 10 years ago in reply to Lev Urusov

Prodigy 200 points

Ok, problem seems to be found, my board was running off a 25MHz crystal and the gel-file was only setup for BBB which uses 24MHz.

There was an error message thrown, but the script did not terminate so I did not see it.

Once I added the 25MHz config, I got relevant numbers and also the EDMA test passes.

So for others using this software, be aware of the configuration if you do not use 24MHz

I only have a 800MHz version of the processor, so I can not run at 1GHz, but here is the section that I use to configure the PLLs:

In the 'hotmenu ARM_OPP100_Config()' section I added this code:

else if(CLKIN==25)
{
   MPU_PLL_Config( CLKIN, 24, 500, 1);
   CORE_PLL_Config( CLKIN, 24, 500, 10, 8, 4);
// DDR3 400MHz setting
// DDR_PLL_Config( CLKIN, 24, 400, 1);
// DDR3 303MHz setting
   GEL_TextOut("**** Setting DDR PLL to 303MHz ......... \n","Output",1,1,1);
   DDR_PLL_Config( CLKIN, 24, 303, 1);
   PER_PLL_Config( CLKIN, 24, 960, 5);
   DISP_PLL_Config( CLKIN, 24, 48, 1);
   GEL_TextOut("**** AM335x ALL ADPLL Config for OPP == OPP100, 25MHz input is Done ......... \n","Output",1,1,1);
}

/PA

0 Biser Gatchev-XID over 10 years ago in reply to PA Nilsson

TI__Guru**** 393215 points

Thanks for the update PA!

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"Optimum" values of DDR3 slave ratio does not work