DDR3 leveling problem 0x000 optimum value

Hi! My writing in English is poor, so I beg your pardone.

- CPU : AM3352BZCZA60 : initialize OPP100
- DDR3 : Micron MT41K256M16HA-125:E (same as at beaglebone black) : run 303MHz
- Using CCS V6, TMS320-XDS1000V3+ emulator
- Ratioseed tool, DDR3 timing configuration tool, BeagleBoneBlack GEL file
  : from processors.wiki.ti.com/.../Sitara_Linux_Training:_Tuning_the_DDR3_Timings_on_BeagleBoneBlack

- My GEL source, I rewrite.
#define  CMD_PHY_CTRL_SLAVE_RATIO            0x100
#define  CMD_PHY_INVERT_CLKOUT                  0x01
#define  DATA_PHY_RD_DQS_SLAVE_RATIO     0x40
#define  DATA_PHY_FIFO_WE_SLAVE_RATIO    0xF4  //RD DQS GATE
#define  DATA_PHY_WR_DQS_SLAVE_RATIO    0x7F
#define  DATA_PHY_WR_DATA_SLAVE_RATIO  0x80  //WRITE DATA
#define  DDR_IOCTRL_VALUE                              (0x18B)

#define ALLOPP_DDR3_READ_LATENCY    0x07             //RD_Latency = (CL + 2) - 1
#define ALLOPP_DDR3_SDRAM_TIMING1   0x0888A39B  
#define ALLOPP_DDR3_SDRAM_TIMING2   0x26337FDA  
#define ALLOPP_DDR3_SDRAM_TIMING3   0x501F830F
#define ALLOPP_DDR3_SDRAM_CONFIG    0x61C05332  //termination = 1 (RZQ/4)
                                                                                                //dynamic ODT = 2 (RZQ/2)
                                                                                                //SDRAM drive = 0 (RZQ/6)
                                                                                                //CWL = 0 (CAS write latency = 5)
                                                                                                //CL = 4 (CAS latency = 6)
                                                                                                //ROWSIZE = 6 (15 row bits)
                                                                                                //PAGESIZE = 2 (10 column bits)
#define ALLOPP_DDR3_REF_CTRL             0x0000093B   //303 * 7.8us = 0x93B
#define ALLOPP_DDR3_ZQ_CONFIG           0x50074BE4

I did all procedure same as listed above link, but I got 0x000 optimum values.
Toggling "PHY_INVERT_CLKOUT", got same results.

By surfing in TI E2E, I see the skew restrictions in routing DDR3 traces.
My design's skew are :
- ADDR_CTRL
  . CK to CKn : 3mils
  . CLock to other net : Max 70mils
- DQ0 net
  . DQS to DQSn : 7mils
  . DQS to DQ0 : 110mils
- DQ1 net
  . DQS to DQSn : 4mils
  . DQS to DQ1 : 110mils
My design's skew violations are 70mil at ADDR_CTRL, 110mil at DQx.

Here is my question,
Can the skew violations causing 0x000 optimum value?
And if there are any solutions about 0x000 optimum value problem, please inform me.

Please be kindly help me!
Thanks.