• State Resolved
  • Locked Locked
  • Replies 14 replies
  • Answers 4 answers
  • Subscribers 97 subscribers
  • Views 1086 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM3352: After DDR leveling, Optimum value get 0

Ronak Parmar
Intellectual 280 points

Part Number: AM3352

We are facing the issue of DDR leveling.We are using SOC:- AM3352 and  DDR3:- H5TQ4G63EFT-RDC.

I want to ask one question that issue may due to CK and DQS length difference?

CK:-635 mil

DQS0:-1100 mil

DQS1:-1093 mil

Please suggest !!

Thanks,

Ronak

  • 0
    TI__Guru**** 393215 points
    Please post the Excel spreadsheet and output log of the leveling procedure.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 280 points

    Hi Biser,

    Thanks for instant support!!

    Please find the atatched files.

    Fullscreen levelingLog.txt Download 
    [CortxA8] 
Enter the PHY_INVERT_CLKOUT value (0 or 1) from the spreadsheet
1

Enter the Seed RD_DQS_SLAVE_RATIO Value in Hex to search the RD DQS Ratio Window
40

Enter the Seed FIFO_WE_SLAVE_RATIO Value in Hex to search the RD DQS Gate Window
f4

Enter the Seed WR_DQS_SLAVE_RATIO Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
77

***************************************************************
	The Slave Ratio Search Program Values are... 
***************************************************************
PARAMETER                       MAX  |  MIN  | OPTIMUM |  RANGE	
***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO    0x000 | 0x000 |  0x000  | 0x000
DATA_PHY_FIFO_WE_SLAVE_RATIO   0x000 | 0x000 |  0x000  | 0x000
DATA_PHY_WR_DQS_SLAVE_RATIO    0x000 | 0x000 |  0x000  | 0x000
DATA_PHY_WR_DATA_SLAVE_RATIO   0x000 | 0x000 |  0x000  | 0x000
***************************************************************
rd_dqs_range = 0
fifo_we_range = 0
wr_dqs_range = 0
wr_data_range = 0

Optimal values have been found!!

***************************************************************
	The Slave Ratio Search Program Values are... 
***************************************************************
PARAMETER                       MAX  |  MIN  | OPTIMUM |  RANGE	
***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO    0x000 | 0x000 |  0x000  | 0x000
DATA_PHY_FIFO_WE_SLAVE_RATIO   0x000 | 0x000 |  0x000  | 0x000
DATA_PHY_WR_DQS_SLAVE_RATIO    0x000 | 0x000 |  0x000  | 0x000
DATA_PHY_WR_DATA_SLAVE_RATIO   0x000 | 0x000 |  0x000  | 0x000
***************************************************************

===== END OF TEST =====

  • 0 in reply to Ronak Parmar
    TI__Guru* 96061 points
    Ronak, you shouldn't have to run leveling if you have a point to point topology, which it looks like you have. Try using the values straight from the RatioSeed spreadsheet. You may also have to adjust READ_LATENCY in the GEL +1.

    Regards,
    James
  • 0 in reply to JJD
    Intellectual 280 points
    Hi James,

    Thanks for reply to us!!

    Can you say that issue come due to trace length difference of following signal?\

    CK:-635 mil

    DQS0:-1100 mil

    DQS1:-1093 mil

    Please confirm!!

    Thanks,
    Ronak
    Hardware Design Engineer
  • 0 in reply to Ronak Parmar
    TI__Guru* 96061 points
    Ronak, the trace length difference is not necessarily the cause of the issue. Did you try the suggestion above?

    Regards,
    James
  • 0 in reply to JJD
    Intellectual 280 points
    Hi James,

    Thanks to reply us.

    We have already tried that kind of iteration but couldn't get proper converge value.

    Can you say that issue occur due to 42E impedance at inner layer instead of 50E?

    Actually we have 50E impedance at top and bottom layer. At inner layer, that value is 42E due to some pcb material die electric constant.

    Please suggest!!

    Thanks,
    Ronak
  • 0 in reply to Ronak Parmar
    TI__Guru* 96061 points
    Ronak, i don't know if the impedance mismatch is the cause of your issue. The suggestion above doesn't require anything to converge. Just use the RatioSeed spreadsheet values directly in your GEL and test the memory. You don't need to run the leveling algorithm.

    REgards,
    James
  • 0 in reply to JJD
    Intellectual 280 points
    Hi James,

    We have tried with ratio seed values directly but in that case board can not boot up.

    Please suggest !!

    Thanks,
    Ronak
  • 0 in reply to Ronak Parmar
    TI__Guru* 96061 points
    Ronak, are you able to perform a test in CCS? Can you peek/poke the memory window to see if it is stable. There is also a memory test script you can run.

    Regards,
    James
  • 0 in reply to JJD
    Intellectual 280 points
    Hi James,

    We have observed that leveling done successful with READ LATENCY 8. It returns 00 value with READ LATENCY 7.

    Can you confirm the equation for READ LATENCY?

    It is CL+2-1 or CL+2?

    In reference manual of AM3352, i have found confusion at PHY_CTRL_1 resister.

    Please confirm.

    Thanks,
    Ronak
  • 0 in reply to JJD
    Intellectual 280 points
    Hi James,

    We are able to DDR leveling with read latency 8. But with read latency 7 we are getting 0 return value.

    Please suggest!!

    Thanks,
    Ronak
  • 0 in reply to Ronak Parmar
    TI__Guru* 96061 points
    Ronak, yes, as stated earlier, you need to add +1 to the read latency with invert clock =1. So read latency 8 is correct.

    REgards,
    james
  • 0 in reply to JJD
    Intellectual 280 points

    Hi James,

    Thanks for your support !!

    You are right that read latency resistor is CL+2 for invert clock=1.

    Thanks,

    Ronak