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AM335X PinMux Conflict for SRAM and 2 Ethernet port

I am configuring for AM335X ZCZ package for peripherals as blow, but always have conflicts. The SRAM and 2 Ethernet always not working together, and two full UARTs.

Thanks,

Frank

1) DDR3 or DDR2
2) 16 bit async SRAM
3) 2 Ethernet
4) 2 full control UART (RX, TX, RTS, CTS, DTR, DSR, DCD)
5) 1 UART with TX RX only
6) 2 CAN
7) 1 eMMC
8) 1 micro SD
9) 2 SPI
10) 2 USB (slave)

  • Based on this description it's not clear what your problem is. Please provide more details.
  • Hi Biser,

    Thanks for looking at my case. I attached the .pinmux file with some conflict inside.

    1) The major issue is SRAM is always have conflict with the 2 Ethernet MII. 

    2) the system is not happy after I want add eMMC like BBB with addition micro SD card.

    3) The two SPIs has conflict

    4) three UART (two with flow control, on TX/RX only) has conflict

    Please have a look.

    Thanks,

    Frank

    AM335x_Design.pinmux.txt

  • Which pinmux tool are you using? I cannot open this.
  • Hi Biser,

    Please rename the file name by deleting .txt at the end. The system doesn't allow .pinmux file to upload. I am using the online tool at dev.ti.com

    Thanks,

    Frank

  • I'm sorry, for some reason I cannot access the Cloud tool from my location. I have tried opening the file in the offline tool, but it doesn't work.
  • Hi Biser,

    What tool you are using? I downloaded the windows tools at

    http://processors.wiki.ti.com/index.php/TI_PinMux_Tool

    And I can load the .pinmux file without problem.

    Frank

  • Frank Wu95 said:
    4) three UART (two with flow control, on TX/RX only) has conflict

    I can't open your file since I don't use windows, but if you get any complaints about I/O set violations for the UARTs then I'm pretty sure you can ignore them: as far as I know I/O sets for UARTs are nonsense since the signals of an UART are asynchronous to each other.

    As for pin allocation... sounds like a tough puzzle. You want a lot of interfaces on a rather small processor. I can't really say whether it can fit or not since some of your requirements are still too vague, in particular those of the SRAM.

  • v4.0.959 (standalone version for Windows).
  • Hi Biser,
    I installed the same version: V4.0.959. and I have one pin conflict left, see attached .pinmux file. Please remove .txt before open it.

    1)       DDR3/DDR2/DDR/SDRAM
    2)       GPMC Dat[0…15] Add[0..19] with 3 CS
    3)       2 Ethernet (10/100)
    4)       2 full control UART (RX, TX, RTS, CTS)
    5)       1 UART with TX RX only
    6)       2 CAN
    7)       1 eMMC (8bit) / or NAND flash
    8)       1 micro SD (4bit)
    9)       1 SPI
    10)    2 USB (slave)

    Thanks,

    Frank

    AM335x_best.pinmux.txt

  • Thanks for looking into my case. I can clarify the SRAM request in itme 1), and I get conflict when using the flowing interfaces. The I am thinking of use NAND flash instead of 3) eMMC. And is there a reference design somewhere?
    1)       GPMC Dat[0…15] Add[0..20] with 3 CS
    2)       2 Ethernet (10/100)
    3)       1 eMMC (8bit)
    4)       1 micro SD (4bit)

    Frank
  • First you must decide what will be your boot devices. For example, there are restrictions for using eMMC on MMC0 and SD on MMC1.
  • NAND flash is attached to the GPMC. See section 7.1 of the AM335X TRM Rev. L. Also check section 26.1.7.4 if you intend to boot from NAND.
  • Hi Biser,

    I want to boot up sequence to be 1) removable storage - micro SD card or if possible USB then micro SD; 2) permernent storage - eMMC or NAND. 

    From the boot sequence list SYSBOOT[4:0], below are some options I found.

    1) 00100b: micro SD (MMC0) -> NAND

    2) 00111b: micro SD (MMC0) -> NAND

    3) 11100b:  eMMC(MMC1) with out card insert; 11000b: micro SD (MMC0) card insert.

    In 3), I can use CD from micro SD card to drive SYS BOOT2 low to make MMC0 boot first, but I cannot fix pin conflict issue and enjoy eMMC benefit. 

    Thanks,

    Frank

  • It's impossible to combine GPMC and booting from eMMC in the same design. Your option would be to plan for NAND boot.
  • Hi Biser,

    I am trying to use ICE v2.1 as reference design and use NAND boot to replace NOR. I found the following issues,

    http://processors.wiki.ti.com/images/f/fb/Tmdsice3359_3h0013_sch_rev2_1a.zip

    1) there is no enough address pin on GPMC for addr 16-19, and v2.1 schematic shows it using addr 6-9 pins to replace them for NOR bus. And I need to access SRAM 16x19, and should use same way. Then, how to access the memory using this special connection? should I use addr 6-9 pins as GPIO to control the addr 16-19?

    2) I have to remove PRI_MMI1_COL, which is used by GPMC wait0, then will it be a problem to use IEEE1588 on this Ethernet port?

    See attached pinmux file, please remove .txt first.

    Thanks,

    FrankAM335x_ICE.pinmux.txt

  • Please describe what kind of end product you want to design. Is this an industrial device, on which you will run industrial networking protocols under SYS/BIOS, or a device which will run Linux. If it's the second case the ICE board may not be the best starting point, since it's designed for industrial applications only and there is no Linux support for it.
  • Hi Biser,

    It is industrial device, but running on Linux. We have industrial protocols running one Liunx, but we want to take advantage to PRU to improve the performance if possible.  I would like to use PRU+MII rather than RMII from CPU to support it . And we might need IEEE1588. 

    Thanks,

    Frank

  • Hi Biser,

    Are you talking about case described in the post below? Then, we should be OK to use eMMC on MMC1 since we are using DDR not GPMC to run the system. And we use GPMC during run time. And I want to ask my last question again. Do you think we can add some external part to fix pin mux issue to use eMMC?

    Frank

    3) 11100b:  eMMC(MMC1) with out card insert; 11000b: micro SD (MMC0) card insert.

    In 3), I can use CD from micro SD card to drive SYS BOOT2 low to make MMC0 boot first, but I cannot fix pin conflict issue and enjoy eMMC benefit. 

    GPMC and MMC1 - Processors forum - Processors - TI E2E support forums

    e2e.ti.com
    Hi, in TRM (26.1.7.5.2) : * If MMC1 is used the GPMC interface is not usable, due to pin muxing options. Could someone clarify, what "not usable" means ?

  • Frank Wu95 said:
    Do you think we can add some external part to fix pin mux issue to use eMMC?

    No, there is no way to switch between MMC1 and GPMC runtime.

  • In ICE v2.1 schematic, NOR flash is address is AD0-AD15 and 4 more GPIOs. Is that mean ICE don't have continuous memory and use GPIOs to switch pages. If not, how does it work; if it is true, then do we have low level driver to deal with pages?

    Frank

  • Yes, this is correct. However the Linux SDK does not support the ICE board, so there is no Linux driver support for this use case.
  • Hi Biser,

    Do we have ICE page support driver source code?

    Mean while, I am trying to use RMII x 2, and it has conflict with GPMC wpn, see attachement. I think wpn is used for NAND flash, do you think I can use other GPIO?

    Thanks,

    FrankAM335x_RMII_GPMC_WPNissue.pinmux.txt

  • Frank Wu95 said:
    Do we have ICE page support driver source code?

    This should be in the Industrial SDK: http://www.ti.com/tool/sysbiossdk-ind-sitara 

    Frank Wu95 said:
    Mean while, I am trying to use RMII x 2, and it has conflict with GPMC wpn, see attachement. I think wpn is used for NAND flash, do you think I can use other GPIO?

    WPn is the write-protect signal. The GPMC_WPn output pin value is controlled through the GPMC_CONFIG[4] WRITEPROTECT bit, which is common to all CS. You could modify software to toggle a GPIO when it toggles this register bit.