Data transfer from FPGA to C6678 over DMA

bt yang

Hi All:

I am trying to perform a data transfer from FPGA(K7) to C6678 over DMA, C6678 as RC, FPGA as EP.

FPGA load a PCIE DMA CORE, communicate with C6678 directly, RefClock= 100M, linkSpeed=2.5G, lane num = 1.

Firstly, I initial the C6678 PCIE follow the example: "C:\ti\pdk_C6678_1_1_2_6\packages\ti\drv\pcie\example\sample\pcie_sample.c".

The setup as follows:

gpPCIE_RC_regs->BAR[1]= 0x90000000;

gpPCIE_app_regs->INBOUND_TRANSLATION[0].IB_BAR = 1;

gpPCIE_app_regs->INBOUND_TRANSLATION[0].IB_START_LO = 0x90000000;

gpPCIE_app_regs->INBOUND_TRANSLATION[0].IB_START_HI = 0x00000000;

gpPCIE_app_regs->INBOUND_TRANSLATION[0].IB_OFFSET = 0x00000000;

gpPCIE_app_regs->CMD_STATUS |= (CSL_PCIESS_APP_CMD_STATUS_IB_XLT_EN_MASK);

gpPCIE_app_regs->OUTBOUND_TRANSLATION[0].OB_OFFSET_INDEX = 0x70000001;

gpPCIE_app_regs->OUTBOUND_TRANSLATION[0].OB_OFFSET_HI = 0x0;

gpPCIE_app_regs->CMD_STATUS |= (CSL_PCIESS_APP_CMD_STATUS_OB_XLT_EN_MASK);

And, PCIE link training successfully with FPGA, and I can read the FPGA configuration space too.

Then, I config the FPGA's configuration space as follow:

gpPCIE_remote_EP_regs->BAR[0] = 0x70000000;
gpPCIE_remote_EP_regs->STATUS_COMMAND |= 0x00000006;

And, C6678 can read & write FPGA MEMORY SPACE successfully by PCIE.

Finally, I config the FPGA DMA CORE throught PCIE, such as: ADDR(0x00801000),SIZE(63),COUNT(129), then START DMA.

I can see The FPGA send the TLP packets successfully by ChipScope, However, I can't read the correct values in ADDR(0x00801000).

What's the matter? Do I miss any thing?

Does the C6678 need to start EDMA?

Who can help me?The project is very urgent.

Looking forward to your reply.

many Thanks

btyang

over 9 years ago

0 Raja over 9 years ago

TI__Guru* 81335 points

Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

Due to holidays and timebank response may be delayed. Thank you for your patience.

0 bt yang over 9 years ago in reply to Raja

Prodigy 155 points

Dear Raja:

Firstly, I am glad to receive your reply!

Secondly, I have aready downloaded the MCSDK KeyStone I, And It is not very helpful to me.

Please notice that the C6678 can read and write FPGA registers correctly throught PCIE.

Now, The only problem is C6678 can't get the datas that FPGA transfered OVER PCIE DMA.

So, can you give me any suggestions about that?

Many Thanks!

yours yang

0 bt yang over 9 years ago in reply to bt yang

Prodigy 155 points

Is there anyone can help me?

0 Ganapathi Dhandapani95 over 9 years ago in reply to bt yang

TI__Mastermind 28085 points

Hi,

The MCSDK PDK PCIe sample example only used for validate the TI PCIe driver. Please refer the PCIe Linux host loader demo example, it support DMA transfer via pcie. For more information about this example refer the readme.pdf under document folder.

MCSDK Path: \ti\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie

Also refer the PCI Express (PCIe) Resource Wiki link:
processors.wiki.ti.com/.../PCI_Express_(PCIe)_Resource_Wiki_for_Keystone_Devices

Thanks,

0 bt yang over 9 years ago in reply to Ganapathi Dhandapani95

Prodigy 155 points

Hi, Dear Ganapathi:

Thanks for your reply!

I saw the PCIe Linux host loader demo example, It showed the transfer from GPP to DSP using DSP's EDMA.

However, my situation is that The C6678 is RC, and the FPGA is EP.At the same time, The FPGA use DMA to transfer the data to DSP.

I think it is different. Yeah?

I thought the C6678 only need to tell the FPGA the memory address of itself, and FPGA will write the C6678's memory directly throught

TLPs. Is it right?

My setup is as follow:

gpPCIE_RC_regs->BAR[1]= 0x90000000;

gpPCIE_app_regs->INBOUND_TRANSLATION[0].IB_BAR = 1;

gpPCIE_app_regs->INBOUND_TRANSLATION[0].IB_START_LO = 0x90000000;

gpPCIE_app_regs->INBOUND_TRANSLATION[0].IB_START_HI = 0x00000000;

gpPCIE_app_regs->INBOUND_TRANSLATION[0].IB_OFFSET = 0x00000000;

gpPCIE_app_regs->CMD_STATUS |= (CSL_PCIESS_APP_CMD_STATUS_IB_XLT_EN_MASK);

And, I set the memory address as 0x90801000 to FPGA. Then, the FPGA will send the TLP to C6678, and the address region is 0x90801000.

The Inbound translation is " local memory address = (0x90801000 - 0x90000000) + 0x00000000 = 0x00801000", Is it right?

But, I can't find the data in 0x00801000.

Or, I must use the EDMA in C6678? then, what is the steps? Start the EDMA in C6678, then start the FPGA's DMA?

Please give me some suggestions about that, thanks a lot!

your's

yang

0 bt yang over 9 years ago in reply to Ganapathi Dhandapani95

Prodigy 155 points

Hi, Dear Ganapathi:

I am so glad to receive your reply. And I saw the PCIe Linux host loader demo example.

It shows the GPP to DSP using DSP's EDMA.

However, my situation is FPGA send DMA TLPs to DSP.

I think the DSP just only need tell the FPGA the memory address inside it.

Then, The FPGA will access the DSP's memory through the DSP's PCIE Inbound ATU.

My setup is as follow:

gpPCIE_RC_regs->BAR[1]= 0x90000000;

gpPCIE_app_regs->INBOUND_TRANSLATION[0].IB_BAR = 1;

gpPCIE_app_regs->INBOUND_TRANSLATION[0].IB_START_LO = 0x90000000;

gpPCIE_app_regs->INBOUND_TRANSLATION[0].IB_START_HI = 0x00000000;

gpPCIE_app_regs->INBOUND_TRANSLATION[0].IB_OFFSET = 0x00000000;

gpPCIE_app_regs->CMD_STATUS |= (CSL_PCIESS_APP_CMD_STATUS_IB_XLT_EN_MASK);

And, I setup the FPGA's DMA address is 0x90801000, then, the translated address is 0x90801000-0x90000000 + 0x00000000 = 0x00801000.

The FPGA can send the TLP packet with the address 0x90801000, but, I can't find the right data in address 0x00801000.

Must I need the C6678's EDMA? I think if FPGA send data through DMA TLP, then C6678 does't need do anything.

Is it right???

Pls give me some suggestions about that.

your's

yang

0 bt yang over 9 years ago in reply to Ganapathi Dhandapani95

Prodigy 155 points

Hi, Ganapathi:

Today, I setup my C6678 as followed:

1. gpPCIE_RC_regs->BAR[1]= 0x00801000; //set Bar Address
2. gpPCIE_app_regs->CMD_STATUS &= (~CSL_PCIESS_APP_CMD_STATUS_IB_XLT_EN_MASK); //disabled the Inbound translation
3. set FPGA's dma address register:

UL TLPWriteBufferArea[MAX_DMA_TRANSFER + 4096];
addr = ((UL) (TLPWriteBufferArea));
*(UL*)(0x60000000+ WRITE_ADDR_OFFSET) = addr & 0xFFFFFFFC; //addr

It does not work!

As metioned in chapter 1.3 "Outbound and Inbound Payload Size" of document <sprabk8.pdf>:
"
Outbound transfer means the local device initiates the transactions to write to or read
from the external device. The CPU or the device-level EDMA is used for outbound data
transfer. The PCIe module does not have built-in EDMA.

Inbound transfer means the external device init iates the transactions to write to or read
from the local device. The PCIe module has a master port to transfer the data to or from
the device memory; no CPU or EDMA is needed for inbound transfer in the local
device.
"

I thought DSP starts FPGA's DMA transfer, FPGA send TLPs to DSP, then FPGA can access DSP's memory directly.

Where I was wrong?

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Data transfer from FPGA to C6678 over DMA