This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM335x GPMC device tree configuration for SRAM access

Other Parts Discussed in Thread: BEAGLEBONE

Hi

I need to configure a device tree (dts) for AM335x ( BeagleBone Black ) GPMC to access a 16 bits data, 1Mbytes SRAM ( Static RAM memory ), with NO multiplexed address with data. Where can I find information about device tree codification for this GPMC configuration?

Thank you

Sergio

  • Hi Sergio,

    I am not aware of a TI example code for this specific use case.

    However you can see what each of the parameters in the GPMC dts nodes is used for in Documentation/devicetree/bindings/memory-controller/omap-gpmc.txt (I am attaching the file here: 

    omap-gpmc.txt
    Device tree bindings for OMAP general purpose memory controllers (GPMC)
    
    The actual devices are instantiated from the child nodes of a GPMC node.
    
    Required properties:
    
     - compatible:		Should be set to one of the following:
    
    			ti,omap2420-gpmc (omap2420)
    			ti,omap2430-gpmc (omap2430)
    			ti,omap3430-gpmc (omap3430 & omap3630)
    			ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
    			ti,am3352-gpmc   (am335x devices)
    
     - reg:			A resource specifier for the register space
    			(see the example below)
     - ti,hwmods:		Should be set to "ti,gpmc" until the DT transition is
    			completed.
     - #address-cells:	Must be set to 2 to allow memory address translation
     - #size-cells:		Must be set to 1 to allow CS address passing
     - gpmc,num-cs:		The maximum number of chip-select lines that controller
    			can support.
     - gpmc,num-waitpins:	The maximum number of wait pins that controller can
    			support.
     - ranges:		Must be set up to reflect the memory layout with four
    			integer values for each chip-select line in use:
    
    			   <cs-number> 0 <physical address of mapping> <size>
    
    			Currently, calculated values derived from the contents
    			of the per-CS register GPMC_CONFIG7 (as set up by the
    			bootloader) are used for the physical address decoding.
    			As this will change in the future, filling correct
    			values here is a requirement.
    
    GPMC DMA information.
     - dmas			GPMC dma channel
     - dma-names		Must be set to "rxtx"
    
    Timing properties for child nodes. All are optional and default to 0.
    
     - gpmc,sync-clk-ps:	Minimum clock period for synchronous mode, in picoseconds
    
     Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2:
     - gpmc,cs-on-ns:	Assertion time
     - gpmc,cs-rd-off-ns:	Read deassertion time
     - gpmc,cs-wr-off-ns:	Write deassertion time
    
     ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3:
     - gpmc,adv-on-ns:	Assertion time
     - gpmc,adv-rd-off-ns:	Read deassertion time
     - gpmc,adv-wr-off-ns:	Write deassertion time
    
     WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
     - gpmc,we-on-ns	Assertion time
     - gpmc,we-off-ns:	Deassertion time
    
     OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
     - gpmc,oe-on-ns:	Assertion time
     - gpmc,oe-off-ns:	Deassertion time
    
     Access time and cycle time timings (in nanoseconds) corresponding to
     GPMC_CONFIG5:
     - gpmc,page-burst-access-ns: 	Multiple access word delay
     - gpmc,access-ns:		Start-cycle to first data valid delay
     - gpmc,rd-cycle-ns:		Total read cycle time
     - gpmc,wr-cycle-ns:		Total write cycle time
     - gpmc,bus-turnaround-ns:	Turn-around time between successive accesses
     - gpmc,cycle2cycle-delay-ns:	Delay between chip-select pulses
     - gpmc,clk-activation-ns: 	GPMC clock activation time
     - gpmc,wait-monitoring-ns:	Start of wait monitoring with regard to valid
    				data
    
    Boolean timing parameters. If property is present parameter enabled and
    disabled if omitted:
     - gpmc,adv-extra-delay:	ADV signal is delayed by half GPMC clock
     - gpmc,cs-extra-delay:		CS signal is delayed by half GPMC clock
     - gpmc,cycle2cycle-diffcsen:	Add "cycle2cycle-delay" between successive
    				accesses to a different CS
     - gpmc,cycle2cycle-samecsen:	Add "cycle2cycle-delay" between successive
    				accesses to the same CS
     - gpmc,oe-extra-delay:		OE signal is delayed by half GPMC clock
     - gpmc,we-extra-delay:		WE signal is delayed by half GPMC clock
     - gpmc,time-para-granularity:	Multiply all access times by 2
    
    The following are only applicable to OMAP3+ and AM335x:
     - gpmc,wr-access-ns:		In synchronous write mode, for single or
    				burst accesses, defines the number of
    				GPMC_FCLK cycles from start access time
    				to the GPMC_CLK rising edge used by the
    				memory device for the first data capture.
     - gpmc,wr-data-mux-bus-ns:	In address-data multiplex mode, specifies
    				the time when the first data is driven on
    				the address-data bus.
    
    GPMC chip-select settings properties for child nodes. All are optional.
    
    - gpmc,burst-length	Page/burst length. Must be 4, 8 or 16.
    - gpmc,burst-wrap	Enables wrap bursting
    - gpmc,burst-read	Enables read page/burst mode
    - gpmc,burst-write	Enables write page/burst mode
    - gpmc,device-width	Total width of device(s) connected to a GPMC
    			chip-select in bytes. The GPMC supports 8-bit
    			and 16-bit devices and so this property must be
    			1 or 2.
    - gpmc,mux-add-data	Address and data multiplexing configuration.
    			Valid values are 1 for address-address-data
    			multiplexing mode and 2 for address-data
    			multiplexing mode.
    - gpmc,sync-read	Enables synchronous read. Defaults to asynchronous
    			is this is not set.
    - gpmc,sync-write	Enables synchronous writes. Defaults to asynchronous
    			is this is not set.
    - gpmc,wait-pin		Wait-pin used by client. Must be less than
    			"gpmc,num-waitpins".
    - gpmc,wait-on-read	Enables wait monitoring on reads.
    - gpmc,wait-on-write	Enables wait monitoring on writes.
    
    Example for an AM33xx board:
    
    	gpmc: gpmc@50000000 {
    		compatible = "ti,am3352-gpmc";
    		ti,hwmods = "gpmc";
    		reg = <0x50000000 0x2000>;
    		interrupts = <100>;
    		dmas = <&edma 52>;
    		dma-names = "rxtx";
    		gpmc,num-cs = <8>;
    		gpmc,num-waitpins = <2>;
    		#address-cells = <2>;
    		#size-cells = <1>;
    		ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
    
    		/* child nodes go here */
    	};
    

    You can use this example as a reference to create your custom dts node. 

    There is a gpmc-nor.txt & gpmc-nand.txt examples as well. They are located in Documentation/devicetree/bindings/mtd/

    Also, if you search for GPMC in this forum, you will find plenty of discussions, which will be of use to you, like: 
      

    Hope this helps. 

    Best Regards, 

    Yordan

  • Hi Yordan

    I read your post of Fri,May 15 2015 7:28AM about dts for SRAM that you answered to Marina and have some questions about:

    sram{
    reg = <1 0 0x01000000>; /*CSn1*/

    bank-width = <2>; /* GPMC_CONFIG1_DEVICESIZE(1) */

    /*gpmc,burst-write;*/
    /*gpmc,burst-read;*/
    /*gpmc,burst-wrap;*/
    gpmc,sync-read; /* GPMC_CONFIG1_READTYPE_ASYNC */
    gpmc,sync-write; /* GPMC_CONFIG1_WRITETYPE_ASYNC */
    gpmc,clk-activation-ns = <0>; /* GPMC_CONFIG1_CLKACTIVATIONTIME(2) */
    gpmc,burst-length = <16>; /* GPMC_CONFIG1_PAGE_LEN(2) */
    gpmc,mux-add-data = <2>; /* GPMC_CONFIG1_MUXTYPE(2) */

    gpmc,sync-clk-ps = <20000>; /* CONFIG2 */

    gpmc,cs-on-ns = <0>;
    gpmc,cs-rd-off-ns = <100>;
    gpmc,cs-wr-off-ns = <40>;

    gpmc,adv-on-ns = <0>; /* CONFIG3 */
    gpmc,adv-rd-off-ns = <20>;
    gpmc,adv-wr-off-ns = <20>;

    gpmc,we-on-ns = <20>; /* CONFIG4 */
    gpmc,we-off-ns = <40>;
    gpmc,oe-on-ns = <20>;
    gpmc,oe-off-ns = <100>;

    gpmc,page-burst-access-ns = <20>; /* CONFIG 5 */
    gpmc,access-ns = <80>;
    gpmc,rd-cycle-ns = <120>;
    gpmc,wr-cycle-ns = <60>;
    gpmc,wr-access-ns = <40>; /* CONFIG 6 */
    gpmc,wr-data-mux-bus-ns = <20>;

    /*gpmc,bus-turnaround-ns = <40>;*/ /* CONFIG6:3:0 = 4 */
    gpmc,cycle2cycle-samecsen; /* CONFIG6:7 = 1 */
    gpmc,cycle2cycle-delay-ns = <20>; /* CONFIG6:11:8 = 4 */

    /* not using dma engine yet, but we can get the channel number here */

    };

    Question 1:

    /*gpmc,burst-write;*/
    /*gpmc,burst-read;*/
    /*gpmc,burst-wrap;*/
    These 3 lines commented, means that GPMC will not use burst access?
    If so, then the following line can be commented also, that is right?
    gpmc,page-burst-access-ns = <20>; /* CONFIG 5 */


    Question 2:

    gpmc,cs-rd-off-ns = <100>;
    This declaration means that the time to cs-rd-off-ns will be 100 ns?


    Question 3:

    How to declare that GPMC must not multiplex address with data?
    I need a GPMC configuration that will not multiplex address with data.
    The absence of address/data mux declaration implies that GPMC will not multiplex address/data?


    Excuse me for being so primary in these questions, but, the fact is, I am in the middle of a video grabber cape board for BeagleBone Black development and I need to be sure about these configurations.

    Thank you very much Yordan.

    Sergio
  • Hi Sergio,

    Sorry for the delayed response.
    Question1:
    " - gpmc,burst-wrap Enables wrap bursting
    - gpmc,burst-read Enables read page/burst mode
    - gpmc,burst-write Enables write page/burst mode"
    So yes, commenting these lines will disable the burst access. You CAN comment gpmc,page-burst-access-ns = <20>; /* CONFIG 5 */ as well.

    Question2:
    Here is the explanation for CS Timings:
    " Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2:
    - gpmc,cs-on-ns: Assertion time
    - gpmc,cs-rd-off-ns: Read deassertion time
    - gpmc,cs-wr-off-ns: Write deassertion time"

    Question 3:
    The gpmc,mux-add-data ENABLES this GPMC feature:
    "gpmc,mux-add-data Address and data multiplexing configuration.
    Valid values are 1 for address-address-data
    multiplexing mode and 2 for address-data
    multiplexing mode. "

    So if the gpmc,mux-add-data is not declared in the GPMC dts node, then the driver won't enable address and data multiplexing

    FYI, all of this info is available in kernel documentation: Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt

    Best Regards,
    Yordan
  • Hi Yordan

    Thank you for your kind support.

    The GPMC interface is working fine now as SRAM interface.

    Two more questions please:

    - As GPMC does not multiplex address with data, in the SRAM configuration ( address/data multiplexing consumes time ), I am understanding that this NOMUX ( parallel address/data) configuration is FASTER than any other MUX configuration (assuming not using bursting), is that right?

    - On the other hand, due SRAM characteristics ( address and data in parallel mode ), I can't use BURST MODE in SRAM access, is that right?

    The reason for these questions is that I am searching for the faster way to access my device, because, as a matter of fact, it is not a SRAM ( Static RAM ), but, a video frame FIFO ( sequential memory ), and I need only the RD, OE and CS1 ( and of course, the 16 bit DATA bus ), where all address lines are discarded.

    Sergio
  • Hi Sergio,

    Correct, my understanding is the same.

    Best Regards,
    Yordan
  • Dear Yordan:

    I also need to configure a device tree (dts) for AM335x ( BeagleBone Black ) GPMC to access a 16 bits data, 1Mbytes SRAM ( Static RAM memory ), with NO multiplexed address with data.

    I applied below device tree too, linux kernel is 4.3.13.  but I can not see sram range in /proc/iomem

    &gpmc {
            status = "okay";
            pinctrl-names = "default";
            pinctrl-0 = <&gpmc_pins>;

            #address-cells = <2>;
            #size-cells = <1>;

            /* chip select ranges */
            ranges = <1 0 0x01000000 0x1000000>;

            sram{
                    reg = <1 0 0x01000000>; /*CSn1*/

                    bank-width = <2>;        /* GPMC_CONFIG1_DEVICESIZE(1) */

                    /*gpmc,burst-write;*/
                    /*gpmc,burst-read;*/
                    /*gpmc,burst-wrap;*/
                    gpmc,sync-read;  /* GPMC_CONFIG1_READTYPE_ASYNC */
       ...

     

    my iomem is as below

    root@arm:~# cat /proc/iomem
    40300000-4030ffff : 40300000.ocmcram
    44d00000-44d03fff : umem
    44d80000-44d81fff : dmem
    44e07000-44e07fff : /ocp/gpio@44e07000
    44e09000-44e0901f : serial
    44e0b000-44e0bfff : /ocp/i2c@44e0b000
    44e10620-44e1062f : phy_ctrl
    44e10648-44e1064b : wakeup
    44e10650-44e10653 : gmii-sel
    44e10800-44e10a37 : pinctrl-single
    44e35000-44e35fff : /ocp/wdt@44e35000
    44e3e000-44e3efff : /ocp/rtc@44e3e000
    47401000-474011ff : control
    47401400-474017ff : mc
      47401400-474017ff : mc
    47401800-474019ff : control
    47401c00-47401fff : mc
      47401c00-47401fff : mc
    48022000-4802201f : serial
    48024000-4802401f : serial
    48030100-480304ff : /ocp/spi@48030000
    48038000-48039fff : mpu
    4803c000-4803dfff : mpu
    48042000-480423ff : /ocp/timer@48042000
    48044000-480443ff : /ocp/timer@48044000
    48046000-480463ff : /ocp/timer@48046000
    48048000-480483ff : /ocp/timer@48048000
    4804a000-4804a3ff : /ocp/timer@4804a000
    4804c000-4804cfff : /ocp/gpio@4804c000
    48060000-48060fff : /ocp/mmc@48060000
    480c8000-480c81ff : /ocp/mailbox@480C8000
    4819c000-4819cfff : /ocp/i2c@4819c000
    481a0100-481a04ff : /ocp/spi@481a0000
    481a8000-481a801f : serial
    481aa000-481aa01f : serial
    481ac000-481acfff : /ocp/gpio@481ac000
    481ae000-481aefff : /ocp/gpio@481ae000
    48310000-48311fff : /ocp/rng@48310000
    49000000-4900ffff : /ocp/edma@49000000
    4a100000-4a1007ff : /ocp/ethernet@4a100000
    4a101000-4a1010ff : /ocp/ethernet@4a100000/mdio@4a101000
    4a101200-4a1012ff : /ocp/ethernet@4a100000
    50000000-50001fff : /ocp/gpmc@50000000
    53500000-5350009f : /ocp/aes@53500000
    80000000-9fffffff : System RAM
      80008000-80a39993 : Kernel code
      80aae000-80c5fb2b : Kernel data

  • Dear Sergio: Would you share me your DTS? thank you very much!
  • Hi Tsao

    Follows my DTS. Change txt to dts.

    Be aware that I am using a video FIFO, not a true SRAM, so, in practice, I don't use address bus, only data bus and control bus, but, I think that the configuration in my DTS is OK for a SRAM.

    Sergio

    bdq9100-00A0.txt
    /*
     * Copyright (C) 2016 WARP TECNOLOGIA ( BRAZIL )
     *
     * This program is free software; you can redistribute it and/or modify
     * it under the terms of the GNU General Public License version 2 as
     * published by the Free Software Foundation.
     */
    /dts-v1/;
    /plugin/;
    
    / {
    	compatible = "ti,beaglebone", "ti,beaglebone-black";
    
    	/* identification */
    	part-number = "bdq9100";
    	version = "00A0","A0";
    
    	/* state the resources this cape uses */
    	exclusive-use =
    		/* the pin header uses */
    		"P8.25",	/* gpmc: gpmc_ad0 */
    		"P8.24",	/* gpmc: gpmc_ad1 */
    		"P8.5",		/* gpmc: gpmc_ad2 */
    		"P8.6",		/* gpmc: gpmc_ad3 */
    		"P8.23",	/* gpmc: gpmc_ad4 */
    		"P8.22",	/* gpmc: gpmc_ad5 */
    		"P8.3",		/* gpmc: gpmc_ad6 */
    		"P8.4",		/* gpmc: gpmc_ad7 */
    		"P8.19",	/* gpmc: gpmc_ad8 */
    		"P8.13",	/* gpmc: gpmc_ad9 */
    		"P8.14",	/* gpmc: gpmc_ad10 */
    		"P8.17",	/* gpmc: gpmc_ad11 */
    		"P8.12",	/* gpmc: gpmc_ad12 */
    		"P8.11",	/* gpmc: gpmc_ad13 */
    		"P8.16",	/* gpmc: gpmc_ad14 */
    		"P8.15",	/* gpmc: gpmc_ad15 */
    		"P9.13",	/* gpmc: gpmc_wpn */
    		"P8.21",	/* gpmc: gpmc_csn1 */
    		"P8.18",	/* gpmc: gpmc_clk */
    		"P8.7",		/* gpmc: gpmc_advn_ale */
    		"P8.8",		/* gpmc: gpmc_oen_ren */
    		"P8.10",	/* gpmc: gpmc_wen */
    		"P8.9",		/* gpmc: gpmc_ben0_cle */
    		"P9.41",	/* cssp: clkout2 */
    		"P9.42",	/* cssp: xdma_event_intr2 */
    		"P9.18",	/* cssp: gpio0_4 */
    		"P9.17",	/* cssp: gpio0_5 */
    		"P9.11",	/* cssp: gpio0_30 */
    /*		"P8.20",	 bdq9100: gpio1_31 */
    		"P8.26",	/* bdq9100: gpio1_20 */
    
    		/* the hardware IP uses */
    		"gpio0_4", 
    		"gpio0_5", 
    		"gpio0_30", 
    		"gpmc",
    		"clkout2",
    		"gpio1_31",
    		"gpio1_29",
    		/* the reset pin */
    		"eMMC_RSTn";
    
    	#address-cells = <1>;
    	#size-cells = <1>;
    
    	fragment@0 {
    		target = <&am33xx_pinmux>;
    		__overlay__ {
    
    			gpmc_pins: pinmux_gpmc_pins {
    				pinctrl-single,pins = <
    					0x000 0x30	/* gpmc_ad0.gpmc_ad0 MODE0 | INPUT | PULLUP */
    					0x004 0x30	/* gpmc_ad1.gpmc_ad1 MODE0 | INPUT | PULLUP */
    					0x008 0x30	/* gpmc_ad2.gpmc_ad2 MODE0 | INPUT | PULLUP */
    					0x00C 0x30	/* gpmc_ad3.gpmc_ad3 MODE0 | INPUT | PULLUP */
    					0x010 0x30	/* gpmc_ad4.gpmc_ad4 MODE0 | INPUT | PULLUP */
    					0x014 0x30	/* gpmc_ad5.gpmc_ad5 MODE0 | INPUT | PULLUP */
    					0x018 0x30	/* gpmc_ad6.gpmc_ad6 MODE0 | INPUT | PULLUP */
    					0x01C 0x30	/* gpmc_ad7.gpmc_ad7 MODE0 | INPUT | PULLUP */
    					0x020 0x30	/* gpmc_ad8.gpmc_ad8 MODE0 | INPUT | PULLUP */
    					0x024 0x30	/* gpmc_ad9.gpmc_ad9 MODE0 | INPUT | PULLUP */
    					0x028 0x30	/* gpmc_ad10.gpmc_ad10 MODE0 | INPUT | PULLUP */
    					0x02C 0x30	/* gpmc_ad11.gpmc_ad11 MODE0 | INPUT | PULLUP */
    					0x030 0x30	/* gpmc_ad12.gpmc_ad12 MODE0 | INPUT | PULLUP */
    					0x034 0x30	/* gpmc_ad13.gpmc_ad13 MODE0 | INPUT | PULLUP */
    					0x038 0x30	/* gpmc_ad14.gpmc_ad14 MODE0 | INPUT | PULLUP */
    					0x03C 0x30	/* gpmc_ad15.gpmc_ad15 MODE0 | INPUT | PULLUP */
    					0x074 0x30	/* gpmc_wpn.gpmc_wpn MODE0 | INPUT | PULLUP */ /* WAS MODE 7 */
    					0x080 0x08	/* gpmc_cscn1.gpmc_cscn1 MODE0 | OUTPUT */
    					0x08C 0x28	/* gpmc_clk.gpmc_clk MODE0 | INPUT */
    					0x090 0x08	/* gpmc_advn_ale.gpmc_advn_ale MODE0 | OUTPUT */
    					0x094 0x08	/* gpmc_oen_ren.gpmc_oen_ren MODE0 | OUTPUT */
    					0x098 0x08	/* gpmc_wen.gpmc_wen MODE0 | OUTPUT */
    /*					0x09C 0x08	 gpmc_ben0_cle.gpmc_ben0_cle MODE0 | OUTPUT */
    				>;
    			};
    			bdq9100_config_pins: pinmux_bdq9100_camera_pins {
    				pinctrl-single,pins = <
    					/* clkout2 */
    					0x1B4 0x03	/* xdma_event_intr1.clkout2 MODE3 | OUTPUT clkout2 */
    
    					/* dmar */
    					0x164 0x2e	/* ecap0_in_pwm0_out.xdma_event_intr2 MODE6 | INPUT */
    
    					/* bdq9100 camera */
    /*					0x084 0x37	  gpio1_31 | MODE7 | INPUT | PULLUPEN */
    					0x09C 0x37	/* gpio2_5 | MODE7 | INPUT | PULLUPEN */ 
    					0x07C 0x37	/* gpio1_29 | MODE7 | INPUT | PULLUPEN */ 
    
    				>;
    			};
    		};
    	};
    
    	fragment@1 {
    		target = <&gpmc>;
    		depth = <1>;	/* only create devices on depth 1 */
    
    		#address-cells = <1>;
    		#size-cells = <1>;
    		ranges;
    
    		__overlay__ {
    
    			status = "okay";
    
    			#address-cells = <2>;
    			#size-cells = <1>;
    
    			pinctrl-names = "default";
    			pinctrl-0 = <&gpmc_pins>;
    
    			/* chip select ranges */
    			ranges = <0 0 0x08000000 0x10000000>,	/* bootloader has this enabled */
    				 <1 0 0x18000000 0x08000000>,
    				 <2 0 0x20000000 0x08000000>,
    				 <3 0 0x28000000 0x08000000>,
    				 <4 0 0x30000000 0x08000000>,
    				 <5 0 0x38000000 0x04000000>,
    				 <6 0 0x3c000000 0x04000000>;
    				 
    			camera{
    				compatible = "bdq9100";
    				status = "okay";
    				pinctrl-names = "default";
    				pinctrl-0 = <&bdq9100_config_pins>;
    
    				reg = <1 0 0x01000000>;	/*CSn1*/
    
    				bank-width = <2>;		/* GPMC_CONFIG1_DEVICESIZE(1) */
    
    				gpmc,sync-read;					/* GPMC_CONFIG1_READTYPE_ASYNC */
    				gpmc,sync-write;				/* GPMC_CONFIG1_WRITETYPE_ASYNC */
    				gpmc,clk-activation-ns = <0>;	/* GPMC_CONFIG1_CLKACTIVATIONTIME(2) */
    				gpmc,mux-add-data = <0>;		/* GPMC_CONFIG1_MUXTYPE(0) */
    
    				gpmc,sync-clk-ps = <20000>;		/* CONFIG2 */
    
    				gpmc,cs-on-ns = <0>;
    				gpmc,cs-rd-off-ns = <100>;
    				gpmc,cs-wr-off-ns = <100>;		/*<40>; */
    
    				gpmc,adv-on-ns = <0>;			/* CONFIG3 */
    				gpmc,adv-rd-off-ns = <20>;
    				gpmc,adv-wr-off-ns = <20>;
    
    				gpmc,we-on-ns = <20>;			/* CONFIG4 */
    				gpmc,we-off-ns = <40>;
    				gpmc,oe-on-ns = <20>;
    				gpmc,oe-off-ns = <100>;
    
    				gpmc,page-burst-access-ns = <20>;	/* CONFIG 5 */
    				gpmc,access-ns = <80>;
    				gpmc,rd-cycle-ns = <120>;
    				gpmc,wr-cycle-ns = <60>;
    				gpmc,wr-access-ns = <40>;		/* CONFIG 6 */
    				gpmc,wr-data-mux-bus-ns = <20>;
    
    
    				/* dma channel */
    				dmas = <&edma 20>;
    				dma-names = "bdq";
    
    				/* tw9910 video decoder */
    				bdq-9100,decoder {
    					i2c-adapter = <&i2c2>;
    
    					/* need it to stop the whinning */
    					#address-cells = <1>;
    					#size-cells = <0>;
    
    					/* fake i2c device node */
    					fake_tw9910 {
    						compatible = "techwell,tw9910";
    						reg = <0x44>;
    						
    						/* buswidth e MPOUT */
    						buswidth = <16>;	/* TW9910 em 16 bits */
    						mpout = <6>;		/* MPOUT como FIELD */
    					};
    				};
    
    			};
    
    		};
    	};
    
    };