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C6678 IBIS model error using HyperLynx DDRx Batch simulation

Yuan Fan
Prodigy 60 points
Other Parts Discussed in Thread: TMS320C6678

I am working on TMS320C6678 DDR3 layout SI simulation. I am using HyperLynx 9.1 as simulation tool and IBIS model,  tms320C6678_4_2_1_r1p5b.ibs,  download from ti website.  When I try to run DDRx Batch simulation, I got following error,

Audit for the net: DSP_DDR3_CKP_0 with type: W1_Fast

** Error **: Too many drivers, not allowed in the DDR interface! Driving pins: U2500.A12, U2500.B12

** Info **: Initialization of drivers failed!

I checked the IBIS model file, it seems DDRCLKOUTP0/DDRCLKOUTN0 is not defined as differential pair which caused the problem. 

Is the IBIS model from current product website correct?

 

Thanks, 

-Yuan

PS: I found this post which has an IBIS model file tms320c6678_r1p6.ibs, which looks like be a newer version of IBIS model, anyone can confirm this file is legit to use? Thanks

https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/188854

 

  • 0
    TI__Guru* 81335 points

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

    We will get back to you on the above query shortly. Thank you for your patience.

    Note: We strongly recommend you to create new e2e thread for your queries instead of following up on an old/closed e2e thread, new threads gets more attention than old threads and can provide link of old threads or information on the new post for clarity and faster response.

  • 0 in reply to Raja
    TI__Guru**** 181321 points

    Yuan

    In the tool, you can define one clock signal as positive and other signal as negative, and then generate the differential clock model first.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 60 points

    Hi David,

    Thanks for the help. Do you mean using HyperLynx generate differential clock model? Would you please give me a little more details? Thanks,