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Hello Sir,
#include <gst/gst.h> #include <gst/app/gstappsrc.h> #include <stdint.h> #include <stdio.h> #include <string.h> #include <stdlib.h> #include<gst/video/video.h> #include <gdk-pixbuf/gdk-pixbuf.h> uint8_t b_white[645*485*3]; uint8_t b_black[645*485*3]; GST_DEBUG_CATEGORY (appsrc_pipeline_debug); #define GST_CAT_DEFAULT appsrc_pipeline_debug typedef struct _App App; struct _App { GstElement *pipeline; GstElement *appsrc; GMainLoop *loop; guint sourceid; GTimer *timer; }; App s_app; static gboolean read_data(App *app) { static gboolean white = FALSE; static GstClockTime timestamp = 0; GstBuffer *buffer; guint size; GstFlowReturn ret; size = 640 * 480 * 3; buffer = gst_buffer_new_wrapped_full( 0, (gpointer)(white?b_white:b_black), size, 0, size, NULL, NULL ); white = !white; GST_BUFFER_PTS (buffer) = timestamp; GST_BUFFER_DURATION (buffer) = gst_util_uint64_scale_int (1, GST_SECOND, 4); timestamp += GST_BUFFER_DURATION (buffer); GST_BUFFER_TIMESTAMP(buffer)=timestamp; g_signal_emit_by_name (app->appsrc, "push-buffer", buffer, &ret); gst_buffer_unref (buffer); if (ret != GST_FLOW_OK) { /* something wrong, stop pushing */ printf("error\n"); // g_main_loop_quit (loop); } return TRUE; } static void start_feed (GstElement * pipeline, guint size, App * app) { if (app->sourceid == 0) { GST_DEBUG ("start feeding"); app->sourceid = g_idle_add ((GSourceFunc) read_data, app); } } static void stop_feed (GstElement * pipeline, App * app) { if (app->sourceid != 0) { GST_DEBUG ("stop feeding"); g_source_remove (app->sourceid); app->sourceid = 0; } } static gboolean bus_message (GstBus * bus, GstMessage * message, App * app) { GST_DEBUG ("got message %s", gst_message_type_get_name (GST_MESSAGE_TYPE (message))); switch (GST_MESSAGE_TYPE (message)) { case GST_MESSAGE_ERROR: { GError *err = NULL; gchar *dbg_info = NULL; gst_message_parse_error (message, &err, &dbg_info); g_printerr ("ERROR from element %s: %s\n", GST_OBJECT_NAME (message->src), err->message); g_printerr ("Debugging info: %s\n", (dbg_info) ? dbg_info : "none"); g_error_free (err); g_free (dbg_info); g_main_loop_quit (app->loop); break; } case GST_MESSAGE_EOS: g_main_loop_quit (app->loop); break; default: break; } return TRUE; } int main (int argc, char *argv[]) { App *app = &s_app; GError *error = NULL; GstBus *bus; GstCaps *caps; GstStateChangeReturn ret ; int i=0; // for ( i = 0; i < 385*288; i++) // { // b_black[i] = 0; // b_white[i] = 0xFFFF; // } for ( i = 0; i < 640*480*3; ) { b_black[i] = 0; //rand()%255; i++; b_white[i] = 255; //rand()%255; i++; b_black[i] = 0; //rand()%255; i++; b_white[i] = 255; //rand()%255; i++; b_black[i] = 0; //rand()%255; i++; b_white[i] = 255; //rand()%255; i++; } gst_init (NULL, NULL); GST_DEBUG_CATEGORY_INIT (appsrc_pipeline_debug, "appsrc-pipeline", 0, "appsrc pipeline example"); /* create a mainloop to get messages and to handle the idle handler that will * * feed data to appsrc. */ app->loop = g_main_loop_new (NULL, TRUE); app->timer = g_timer_new(); app->pipeline = gst_parse_launch("appsrc name=mysource ! videoconvert ! vpe num-input-buffers=8 ! queue ! ducatimpeg4enc bitrate=4000 ! queue ! mpeg4videoparse ! rtpmp4vpay config-interval=1 pt=96 ! udpsink host=172.24.129.207 port=5000", NULL); g_assert (app->pipeline); bus = gst_pipeline_get_bus (GST_PIPELINE (app->pipeline)); g_assert(bus); /* add watch for messages */ gst_bus_add_watch (bus, (GstBusFunc) bus_message, app); #if 1 GstVideoInfo info; /* get the appsrc */ app->appsrc = gst_bin_get_by_name (GST_BIN(app->pipeline), "mysource"); g_assert(app->appsrc); g_assert(GST_IS_APP_SRC(app->appsrc)); g_signal_connect (app->appsrc, "need-data", G_CALLBACK (start_feed), app); g_signal_connect (app->appsrc, "enough-data", G_CALLBACK (stop_feed), app); #endif /* set the caps on the source */ #if 1 caps = gst_caps_new_simple ("video/x-raw", "format",G_TYPE_STRING,"RGB", "bpp",G_TYPE_INT,24, "depth",G_TYPE_INT,24, "width", G_TYPE_INT, 640, "height", G_TYPE_INT, 480, "framerate", GST_TYPE_FRACTION, 30, 1, NULL); gst_app_src_set_caps(GST_APP_SRC(app->appsrc), caps); g_object_set (app->appsrc, "format", GST_FORMAT_TIME, NULL); #endif /* go to playing and wait in a mainloop. */ ret = gst_element_set_state (app->pipeline, GST_STATE_PLAYING); if (ret == GST_STATE_CHANGE_FAILURE) { g_printerr ("Unable to set the pipeline to the playing state.\n"); gst_object_unref (app->pipeline); return -1; } /* this mainloop is stopped when we receive an error or EOS */ g_main_loop_run (app->loop); GST_DEBUG ("stopping"); gst_element_set_state (app->pipeline, GST_STATE_NULL); gst_object_unref (bus); g_main_loop_unref (app->loop); return 0; }
Hi Naveen,
Can you please dump ID registers starting from 0x4AE0 C200 , ending 0x4AE0 C214 (last reg)?
I'm not sure it is a silicon issue, but be aware that the latest silicon is 2.0 and it's the recommended one for production.
I also found a similar E2E thread but unfortunately without real solution:
Regards,
Stan
If the application is running fine on 4 boards and have consistently problem with one of the board, board design can be a potential culprit too. Have you done thorough DDR mem testing and ruled out that as culprit? Between black and white and color frame encoding, the encoder will access DDR at higher rate. You can try to reduce the clock speed of IVA and DDR and see if that causes difference in behavior.
Hello Sir,
Please find the attached dump of registers from 0x4AE0 C200 , ending 0x4AE0 C214 (last reg).
Regards
Naveen Shetti
root@dra7xx-evm:~# devmem2 0x4AE0C200 /dev/mem opened. Memory mapped at address 0x76f4d000. Read at address 0x4AE0C200 (0x76f4d200): 0x13008013 root@dra7xx-evm:~# devmem2 0x4AE0C201 /dev/mem opened. Memory mapped at address 0x76f40000. Read at address 0x4AE0C201 (0x76f40200): 0x13008013 root@dra7xx-evm:~# devmem2 0x4AE0C202 /dev/mem opened. Memory mapped at address 0x76f49000. Read at address 0x4AE0C202 (0x76f49200): 0x13008013 root@dra7xx-evm:~# devmem2 0x4AE0C203 /dev/mem opened. Memory mapped at address 0x76fa6000. Read at address 0x4AE0C203 (0x76fa6200): 0x13008013 root@dra7xx-evm:~# devmem2 0x4AE0C204 /dev/mem opened. Memory mapped at address 0x76fa3000. Read at address 0x4AE0C204 (0x76fa3204): 0x1B99002F root@dra7xx-evm:~# devmem2 0x4AE0C205 /dev/mem opened. Memory mapped at address 0x76f13000. Read at address 0x4AE0C205 (0x76f13204): 0x1B99002F root@dra7xx-evm:~# devmem2 0x4AE0C206 /dev/mem opened. Memory mapped at address 0x76fe2000. Read at address 0x4AE0C206 (0x76fe2204): 0x1B99002F root@dra7xx-evm:~# devmem2 0x4AE0C207 /dev/mem opened. Memory mapped at address 0x76f66000. Read at address 0x4AE0C207 (0x76f66204): 0x1B99002F root@dra7xx-evm:~# devmem2 0x4AE0C208 /dev/mem opened. Memory mapped at address 0x76ff1000. Read at address 0x4AE0C208 (0x76ff1208): 0x015D7D96 root@dra7xx-evm:~# devmem2 0x4AE0C209 /dev/mem opened. Memory mapped at address 0x76f02000. Read at address 0x4AE0C209 (0x76f02208): 0x015D7D96 root@dra7xx-evm:~# devmem2 0x4AE0C20a /dev/mem opened. Memory mapped at address 0x76fb1000. Read at address 0x4AE0C20A (0x76fb1208): 0x015D7D96 root@dra7xx-evm:~# devmem2 0x4AE0C20b /dev/mem opened. Memory mapped at address 0x76fd1000. Read at address 0x4AE0C20B (0x76fd1208): 0x015D7D96 root@dra7xx-evm:~# devmem2 0x4AE0C20c /dev/mem opened. Memory mapped at address 0x76fb6000. Read at address 0x4AE0C20C (0x76fb620c): 0x3FBA1100 root@dra7xx-evm:~# devmem2 0x4AE0C20d /dev/mem opened. Memory mapped at address 0x76fa2000. Read at address 0x4AE0C20D (0x76fa220c): 0x3FBA1100 root@dra7xx-evm:~# devmem2 0x4AE0C20e /dev/mem opened. Memory mapped at address 0x76fd0000. Read at address 0x4AE0C20E (0x76fd020c): 0x3FBA1100 root@dra7xx-evm:~# devmem2 0x4AE0C20f /dev/mem opened. Memory mapped at address 0x76ff0000. Read at address 0x4AE0C20F (0x76ff020c): 0x3FBA1100 root@dra7xx-evm:~# devmem2 0x4AE0C210 /dev/mem opened. Memory mapped at address 0x76f84000. Read at address 0x4AE0C210 (0x76f84210): 0x3A0C0121 root@dra7xx-evm:~# devmem2 0x4AE0C211 /dev/mem opened. Memory mapped at address 0x76f49000. Read at address 0x4AE0C211 (0x76f49210): 0x3A0C0121 root@dra7xx-evm:~# devmem2 0x4AE0C212 /dev/mem opened. Memory mapped at address 0x76f6e000. Read at address 0x4AE0C212 (0x76f6e210): 0x3A0C0121 root@dra7xx-evm:~# devmem2 0x4AE0C213 /dev/mem opened. Memory mapped at address 0x76fe4000. Read at address 0x4AE0C213 (0x76fe4210): 0x3A0C0121 root@dra7xx-evm:~# devmem2 0x4AE0C214 /dev/mem opened. Memory mapped at address 0x76f6e000. Read at address 0x4AE0C214 (0x76f6e214): 0x2E6404F0
Naveen,
Is this a separate issue or the same one as before? If same as before, have you now been able to reproduce the same failure on an SR1.1 board that previously you only saw on the SR2.0 board? If so, what are you now doing differently?
Tom