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AM3352: EMIF DDR3 Tuning fails

Marcel Kaus
Prodigy 140 points
Part Number: AM3352

Hi there,

we are using a AM3352 on a custom board that was derived from the Beaglebone. It is using the EMIF with a single MT41K256M16HA-125 Memory Chip. The trace lengths are different to the trace lengths on the Beagleboard. As an SPL we use Uboot to load a Linux Kernel

Due to some errors in the linux device tree file the CPU at first was running with 300Mhz instead of 600Mhz. When the CPU was running with the lower Clock speed there were no Memory issues. With a higher clock speed we noticed that we had some memory issues ( corrupt SCP file transfers, dropped SSH sessions, memtester showed failures, ... ). 

We tried to fix this by tuning the DDR3 timings like described in 

http://processors.wiki.ti.com/index.php/Sitara_Linux_Training:_Tuning_the_DDR3_Timings_on_BeagleBoneBlack

But the Salve Ratio Search Programm only shows 0x0 values all the time. Since we use the same memory chip as the Beaglebone we get the same register values for ALLOP_DDR3_SDRAM_TIMING1-3 as used in the example. Only values for DATAx_PHY_RD DQS_SLAVE_RATIO, DATAx_PHY_FIFO_WE_SLAVE_RATIO and DATAx_PHY_WR DQS_SLAVE_RATIO are different.

Could there be another resaon for getting 0x0 values beside wrong register values in the GEL file?


Also:

Since we already have some devices deployed and don't want to update Uboot on deployed devices we thought of using the EMIF Linux Kernel drivers to change register values when we determined the right DDR3 timings. But the EMIF driver doesn't seem to be doing anything with our current Kernel ( 4.4.21 ).

Can the EMIF drivers be used to change memory timings when the kernel is loaded?


Best regards

Edit:

Xenon_CPU-FPGA-Module_RatioSeed.xlsx

BeagleBlack_400Mhz_4GbDDR_new_rev.gel

AM335x_DDR_register_calc.xls

BeagleBlack_400Mhz_4GbDDR_PHY_INVERT_CLKOUT_0.gel

BeagleBlack_400Mhz_4GbDDR_PHY_INVERT_CLKOUT_0.log
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CortxA8: Output: **** AM335x BeagleBlack Initialization is in progress ..........
CortxA8: Output: **** AM335x ALL PLL Config for OPP == OPP100 is in progress .........
CortxA8: Output: Input Clock Read from SYSBOOT[15:14]: 24MHz
CortxA8: Output: **** Going to Bypass...
CortxA8: Output: **** Bypassed, changing values...
CortxA8: Output: **** Locking ARM PLL
CortxA8: Output: **** Core Bypassed
CortxA8: Output: **** Now locking Core...
CortxA8: Output: **** Core locked
CortxA8: Output: **** DDR DPLL Bypassed
CortxA8: Output: **** DDR DPLL Locked
CortxA8: Output: **** PER DPLL Bypassed
CortxA8: Output: **** PER DPLL Locked
CortxA8: Output: **** DISP PLL Config is in progress ..........
CortxA8: Output: **** DISP PLL Config is DONE ..........
CortxA8: Output: **** AM335x ALL ADPLL Config for OPP == OPP100 is Done .........
CortxA8: Output: **** AM335x DDR3 EMIF and PHY configuration is in progress.........
CortxA8: Output: EMIF PRCM is in progress .......
CortxA8: Output: EMIF PRCM Done
CortxA8: Output: DDR PHY Configuration in progress
CortxA8: Output: Waiting for VTP Ready .......
CortxA8: Output: VTP is Ready!
CortxA8: Output: DDR PHY CMD0 Register configuration is in progress .......
CortxA8: Output: DDR PHY CMD1 Register configuration is in progress .......
CortxA8: Output: DDR PHY CMD2 Register configuration is in progress .......
CortxA8: Output: DDR PHY DATA0 Register configuration is in progress .......
CortxA8: Output: DDR PHY DATA1 Register configuration is in progress .......
CortxA8: Output: Setting IO control registers.......
CortxA8: Output: EMIF Timing register configuration is in progress .......
CortxA8: Output: EMIF Timing register configuration is done .......
CortxA8: Output: DDR PHY Configuration done
CortxA8: Output: **** AM335x BeagleBlack Initialization is Done ******************
[CortxA8]
Enter the PHY_INVERT_CLKOUT value (0 or 1) from the spreadsheet
0
Enter the Seed RD_DQS_SLAVE_RATIO Value in Hex to search the RD DQS Ratio Window
40
Enter the Seed FIFO_WE_SLAVE_RATIO Value in Hex to search the RD DQS Gate Window
6D
Enter the Seed WR_DQS_SLAVE_RATIO Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
0
***************************************************************
The Slave Ratio Search Program Values are...
***************************************************************
PARAMETER MAX | MIN | OPTIMUM | RANGE
***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000
DATA_PHY_FIFO_WE_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000
DATA_PHY_WR_DQS_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000
DATA_PHY_WR_DATA_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000
***************************************************************
rd_dqs_range = 0
fifo_we_range = 0
wr_dqs_range = 0
wr_data_range = 0
Optimal values have been found!!
***************************************************************
The Slave Ratio Search Program Values are...
***************************************************************
PARAMETER MAX | MIN | OPTIMUM | RANGE
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

BeagleBlack_400Mhz_4GbDDR_PHY_INVERT_CLKOUT_1.gel

BeagleBlack_400Mhz_4GbDDR_PHY_INVERT_CLKOUT_1.log
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CortxA8: Output: **** AM335x BeagleBlack Initialization is in progress ..........
CortxA8: Output: **** AM335x ALL PLL Config for OPP == OPP100 is in progress .........
CortxA8: Output: Input Clock Read from SYSBOOT[15:14]: 24MHz
CortxA8: Output: **** Going to Bypass...
CortxA8: Output: **** Bypassed, changing values...
CortxA8: Output: **** Locking ARM PLL
CortxA8: Output: **** Core Bypassed
CortxA8: Output: **** Now locking Core...
CortxA8: Output: **** Core locked
CortxA8: Output: **** DDR DPLL Bypassed
CortxA8: Output: **** DDR DPLL Locked
CortxA8: Output: **** PER DPLL Bypassed
CortxA8: Output: **** PER DPLL Locked
CortxA8: Output: **** DISP PLL Config is in progress ..........
CortxA8: Output: **** DISP PLL Config is DONE ..........
CortxA8: Output: **** AM335x ALL ADPLL Config for OPP == OPP100 is Done .........
CortxA8: Output: **** AM335x DDR3 EMIF and PHY configuration is in progress.........
CortxA8: Output: EMIF PRCM is in progress .......
CortxA8: Output: EMIF PRCM Done
CortxA8: Output: DDR PHY Configuration in progress
CortxA8: Output: Waiting for VTP Ready .......
CortxA8: Output: VTP is Ready!
CortxA8: Output: DDR PHY CMD0 Register configuration is in progress .......
CortxA8: Output: DDR PHY CMD1 Register configuration is in progress .......
CortxA8: Output: DDR PHY CMD2 Register configuration is in progress .......
CortxA8: Output: DDR PHY DATA0 Register configuration is in progress .......
CortxA8: Output: DDR PHY DATA1 Register configuration is in progress .......
CortxA8: Output: Setting IO control registers.......
CortxA8: Output: EMIF Timing register configuration is in progress .......
CortxA8: Output: EMIF Timing register configuration is done .......
CortxA8: Output: DDR PHY Configuration done
CortxA8: Output: **** AM335x BeagleBlack Initialization is Done ******************
Enter the PHY_INVERT_CLKOUT value (0 or 1) from the spreadsheet
1
Enter the Seed RD_DQS_SLAVE_RATIO Value in Hex to search the RD DQS Ratio Window
40
Enter the Seed FIFO_WE_SLAVE_RATIO Value in Hex to search the RD DQS Gate Window
ED
Enter the Seed WR_DQS_SLAVE_RATIO Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
7F
***************************************************************
The Slave Ratio Search Program Values are...
***************************************************************
PARAMETER MAX | MIN | OPTIMUM | RANGE
***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000
DATA_PHY_FIFO_WE_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000
DATA_PHY_WR_DQS_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000
DATA_PHY_WR_DATA_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000
***************************************************************
rd_dqs_range = 0
fifo_we_range = 0
wr_dqs_range = 0
wr_data_range = 0
Optimal values have been found!!
***************************************************************
The Slave Ratio Search Program Values are...
***************************************************************
PARAMETER MAX | MIN | OPTIMUM | RANGE
***************************************************************
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0
    TI__Guru**** 393215 points
    Hi,

    No, EMIF configuration is done once only at the SPL/MLO stage of U-boot. Once the EMIF is started it's impossible to change the settings. I would suggest that you check your DDR_CLK frequency when you run at 300MHz CPU speed compared to 600MHz.
  • 0 in reply to Biser Gatchev-XID
    Prodigy 140 points
    Hi Biser

    Any ideas on the 0x0 values during DDR3 tuning?


    Best Regards.
  • 0 in reply to Marcel Kaus
    TI__Guru**** 393215 points
    Can you post the spreadsheet?
  • 0 in reply to Biser Gatchev-XID
    Prodigy 140 points
    I added them to the original post.
  • 0 in reply to Marcel Kaus
    TI__Guru**** 393215 points
    Can you try with PHY_INVERT_CLKOUT = 1 ?
  • 0 in reply to Biser Gatchev-XID
    Prodigy 140 points
    Since PHY_INVERT_CLKOUT = 1 for Byte 0 and 0 for Byte 1 we tried both.
  • 0 in reply to Marcel Kaus
    TI__Guru**** 393215 points
    I will ask the DDR experts to look at this. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    Prodigy 140 points

    Any news on this?

  • 0 in reply to Marcel Kaus
    TI__Guru**** 393215 points
    Sorry about this delay. I have escalated the request.
  • 0 in reply to Marcel Kaus
    TI__Mastermind 26195 points

    I apologize for the delay, I am talking to apps managers about this one....

  • 0 in reply to Rogerio Almeida
    TI__Expert 8140 points

    Do you have VTT Regulator which is driven by a GPIO ? If so make sure the GPIO is driven high from the gel file.

  • 0
    TI__Genius 9655 points
    Can you share your CCS log files and corresponding GEL File that you used when you obtained 0x0 with the S/W leveling search program? If you have tried with invert_clk=1, please do share the respective files for that setting too.

    Regards, Siva
  • 0 in reply to Shivasharan Nagalikar
    Prodigy 140 points

    We use a TPS6526-1 that isn't driven by GPIO.

  • 0 in reply to sivak
    Prodigy 140 points
    I've added the gel/log files you asked for to the original post.
  • 0 in reply to Marcel Kaus
    Prodigy 140 points
    Could you reproduce the behavior that we see? Do you need some additional information?
  • 0 in reply to Marcel Kaus
    TI__Genius 9655 points

    I'm looking into the issue. Will provide you an update soon.

    Regards, Siva

  • 0 in reply to sivak
    TI__Genius 9655 points
    #1 Please use invert_clkout=1
    #2 As indicated in the tool, when invert_clkout=1, CMDx_PHY_CTRL_SLAVE_RATIO need to be set to 0x100 and 0x80 if invert_clkout=0. In your GEL file with invert_clkout=1, it is set to 0x80. Please correct this
    #3 Additionally, with invert_clkout=1, I'd also suggest to increase the READ_LATENCY programmed in the DDR_PHY_CTRL_1 register by an extra clock cycle. Currently, you have this set to 0x7 (i.e. CL=6). This needs to be changed to 0x8 with invert_clkout=1

    Make the above changes and please try the SW leveling code and let me know what you find.

    Regards, Siva
  • 0 in reply to sivak
    Prodigy 140 points

    The leveling routines now output values:

    ***************************************************************
    The Slave Ratio Search Program Values are...
    ***************************************************************
    PARAMETER MAX | MIN | OPTIMUM | RANGE
    ***************************************************************
    DATA_PHY_RD_DQS_SLAVE_RATIO 0x059 | 0x002 | 0x02d | 0x057
    DATA_PHY_FIFO_WE_SLAVE_RATIO 0x168 | 0x041 | 0x0d4 | 0x127
    DATA_PHY_WR_DQS_SLAVE_RATIO 0x0ca | 0x085 | 0x0a7 | 0x045
    DATA_PHY_WR_DATA_SLAVE_RATIO 0x112 | 0x0ad | 0x0df | 0x065
    ***************************************************************

    I put the Values into the U-Boot memory register variables:

    /* Micron MT41K256M16HA-125E on Xenon*/
#define MT41K256M16HA125E_XENON_EMIF_READ_LATENCY 0x100008
#define MT41K256M16HA125E_XENON_EMIF_TIM1   0x0AAAD4DB
#define MT41K256M16HA125E_XENON_EMIF_TIM2   0x266B7FDA
#define MT41K256M16HA125E_XENON_EMIF_TIM3   0x501F867F
#define MT41K256M16HA125E_XENON_EMIF_SDCFG    0x61C05332
#define MT41K256M16HA125E_XENON_EMIF_SDREF    0xC30
#define MT41K256M16HA125E_XENON_ZQ_CFG    0x50074BE4
#define MT41K256M16HA125E_XENON_RATIO     0x100
#define MT41K256M16HA125E_XENON_INVERT_CLKOUT   0x1
#define MT41K256M16HA125E_XENON_RD_DQS    0x2D
#define MT41K256M16HA125E_XENON_WR_DQS    0xA7
#define MT41K256M16HA125E_XENON_PHY_WR_DATA   0xDF
#define MT41K256M16HA125E_XENON_PHY_FIFO_WE   0xD4
#define MT41K256M16HA125E_XENON_IOCTRL_VALUE    0x18B

    But when i try to run U-Boot

    I either get Errors like :

    Unable to update property /ocp/ethernet@4a100000/slave@4a100200:mac-address, err=FDT_ERR_BADSTRUCTURE
    Unable to update property /ocp/ethernet@4a100000/slave@4a100200:local-mac-address, err=FDT_ERR_BADSTRUCTURE
    Unable to update property /ocp/ethernet@4a100000/slave@4a100300:mac-address, err=FDT_ERR_BADSTRUCTURE
    Unable to update property /ocp/ethernet@4a100000/slave@4a100300:local-mac-address, err=FDT_ERR_BADSTRUCTURE

    or:

    musb-hdrc: kernel must blacklist external hubs
    musb_init_controller failed with status -22
    musb-hdrc: kernel must blacklist external hubs
    musb_init_controller failed with status -22
    Net: data abort

    MAYBE you should read doc/README.arm-unaligned-accesses

    pc : [<9f77c970>] lr : [<9f7a35fc>]
    sp : 9f640ec8 ip : 00000000 fp : 80800020
    r10: 8083ecc1 r9 : 9f640f28 r8 : 00000014
    r7 : 4a100000 r6 : 9f7a1f18 r5 : 9f6412d0 r4 : 9f641318
    r3 : 00000000 r2 : 9f6413e0 r1 : 00000000 r0 : 9f6413cc
    Flags: Nzcv IRQs off FIQs on Mode SVC_32
    Resetting CPU ...

    resetting ...


    Any ideas why this could happen?

  • 0 in reply to Marcel Kaus
    TI__Genius 9655 points
    Did this new error occur when updating the DDR configuration? If not, can you please open a new E2E thread. This seems to be unrelated to the original DDR issue.

    Regards, Siva