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AM3352: EMIF values for twin-die DDR3

Sung-IL
Mastermind 30150 points
Part Number: AM3352

Dear Champs,

My customer develop AM3352 board using twin-die DDR3L - MT41K512M16VRN-107 IT:P.

When I checked below e2e, it seemed it can be ok to connect single-rank twin-die DDR3 memory to AM3352.

Linux/AM3356: External Memory Compatibility Check - Processors forum - Processors - TI E2E support f...

e2e.ti.com
Part Number: AM3356 Tool/software: Linux We're selecting external NAND and DDR3/L for an AM3356 project and we want to check if any of the below devices have been

But, when I try to calculate EMIF values using app. note below, I'm confused what value I should select especially tFAW and tRFC.

As it's basic part is MT41K512M8, I input the parameters from it, but it was colored as red in the EMIF cal. excel file as below.

 

In MT41K512M8, 

https://www.micron.com/products/dram/ddr3-sdram/part-catalog/mt41k512m8da-107-it

I found the page size is 1KB and thus tFAW is 27 as it is 8bit die.

For tRFC, I selected 260ns because single die is 4Gb.

Could you please guide me how I can calculate EMIF values for twin-die case?

My customer failed to access DDR3 memory now, but we could not decided EMIF values yet.

Thanks and Best Regards,

SI.

  • 0
    TI__Guru* 80390 points

    SI, it looks like you have input the timings correctly, but you probably did not fill out the DDR memory specs correctly on the System Details tab.  For the memory your customer chose, it should look like this:

    Detail Description Value Units
    6 Speed Bin: Data Rate 1866 MT/s
    7 Density (per device) 4 Gb
    8 Number of Rows 16 -
    9 Number of Columns 10 -
    10 Number of Banks 8 -
    11 Speed Bin: CAS Latency @ 1866MT/s data rate 13 ntCK
    12 Width (per device) 8 Bits
    13 Average Periodic Refresh Interval 7800 ns

    This should fix the red cells in the spreadsheet.

    Regards,

    James

  • 0 in reply to JJD
    TI__Mastermind 30150 points

    Hi James,

    That is the point. The red cells were removed with this modification you suggested, but I'm not sure if this is right because the device has 8Gb density and 16bit I/F by combining 2 dies.

    I found there is no difference in the EMIF register values with/without your modification, and my customer can access just up to 512MB region of total 1GB region.

    Do you think what should be modified to access remained 512MB of DDR memory?

    Thanks and Best Regards,

    SI.

  • 0 in reply to Sung-IL
    TI__Guru* 80390 points

    Hi SI, I think you may have choose 11 Column bits because the DDR datasheet shows 1K page size per die (10 column bits), but 2 dies would make it 2K pages.  If you set the column bits to 11, this would configure for 2K page size.  Try this out a let me know if this works so i can mention this subtlety in the documentation.

    Regards,

    James

  • 0 in reply to JJD
    TI__Mastermind 30150 points

    Hi James,

    This issue was resolved after modifying ddr.c as mentioned in below e2e.

    https://e2e.ti.com/support/processors/f/791/p/893158/3315182#3315182

    Thanks and Best Regards,

    SI.