Timing requirements for DM648 VLYNQ VCLK

Eddie said:

Are the timing requirements for the VLYNQ VCLK the same as VPxCLKINx (Table 6-50 of SPRS372D.pdf)? 

Max speed is then ~100 MHz?

The VLYNQ clock is actually seperate, the timing requirements for the VLYNQ are actually given in table 6-91 on page 166 of SPRS372E (DM648 Datasheet). Based on the spec, the VLYNQ must run at at least 125MHz (8nS max VCLK cycle time) but no more than 250MHz with the VCLK as input (pulse durations of 2nS minimum high/low) or nor more than 166MHz with the VCLK as output (pulse durations of 3nS minimum high/low).

Eddie said:

Xilinx states that their FPGAs are capable of 285 Mbps with bits on the VLYNQ interface

This is probably with another device, different devices have different VLYNQ capabilities, keep in mind that the clocks mentioned above do not take into account any coding or protocol overhead so the actual bandwith is a bit less.

Dang, how did I miss that table! Sorry to bug you about it.

So the max one directional rate is (4 bits * clk) - coding and protocol overhead. Any guestimates what the bps is?

Thanks Bernie