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TMS320C6672: Input timing of wait signal for EMIF16

UNA
Mastermind 7980 points
Part Number: TMS320C6672


Hi,

I have a question about the assert timing of WAIT signal for C6672.

Q1: Is it defined the timing to assert the WAIT signal after the OE( or WE) singal becomes active?

Q2: The data manual defined about setup time of WAIT signals( #28 and #14 ) on Table 7-76. Does this mean that the WAIT signal must be asserted before 4E + 3 where OE ( or WE) is deasserted?

Best regards,
H.U

  • 0
    TI__Guru**** 161600 points
    Hi,

    We're looking into this. Feedback will be posted here.

    Best Regards,
    Yordan
  • 0
    TI__Guru**** 161600 points
    Hi,

    Q1: Is it defined the timing to assert the WAIT signal after the OE( or WE) singal becomes active?

    Section 7.19 EMIF16 Peripheral defines:
    Setup time, WAIT asserted before WE high
    Setup time, WAIT asserted before OE high

    Q2: The data manual defined about setup time of WAIT signals( #28 and #14 ) on Table 7-76. Does this mean that the WAIT signal must be asserted before 4E + 3 where OE ( or WE) is deasserted?

    This is the maximum time during which the WAIT signal must be asserted and this should happen before WE/OE is high.

    You can refer to Read Timing/Write Timing & Figure 7-53 EMIF16 Asynchronous Memory Read Timing Diagram through Figure 7-56 EMIF16 EM_WAIT Write Timing Diagram.

    Best Regards,
    Yordan
  • 0
    TI__Mastermind 42545 points

    Hi H.U.
    The timing of the wait signal is a little confusing. As noted in the EMIF users guide, when extended wait is enabled, R_STROBE and W_STROBE cannot be set to 0. This will ensure that there are at least two clock cycles (E) for the strobe period of every extended wait access. The WAIT signal should be asserted within the first half clock period of the strobe cycle (E/2) and must be held for at least to clock periods (2E). Once the device deasserts the wait, it must be held in the deasserted state for at least 2 clock periods (2E).
    Often when customers are using the extended wait capability, they will start the cycle with the wait signal asserted based on the CE and the address to ensure that the wait is present as soon as possible. Another scenario is to have the wait asserted as the default state of that signal. In the latter case, the target device will drive the wait signal into the deasserted state to complete the cycle and then allow the wait signal to be asserted again once the access is complete.
    The 4E+3 is not a setup time for the wait signal. That parameter defines the maximum delay between the time the wait is deasserted to the WE or OE going high. Since the external wait signal is asynchronous to the internal clocking of the C6672, it may take up to four clocks for the signal to be sampled and for the access state machine to cycle to the point where the OE and the WE are driven high. This may happen in less time but the maximum is provided.
    Regards,
    Bill

  • 0 in reply to Bill Taboada
    Mastermind 7980 points

    Hi Bill,

    Thank you for your reply.
    I understood the input timing of the Wait signal. but, I am a little confused.

    What are td(WAIT-WEH) [Setup time, WAIT asserted before WE high] and td (WAIT-OEH) [Setup time, WAIT asserted before OE high] in defined for? What is the difference td(WAITH-OEH) [Delay time from WAIT deasserted to OE# high] and td(WAITH-WEH) [Delay time from WAIT deasserted to WE# high]?

    Best regards,
    H.U

  • 0 in reply to UNA
    TI__Mastermind 42545 points

    Hi H.U,

    This timing is included to provide the maximum time that the memory access can be extended from when the WAIT signals goes inactive. We often get questions from customers who are concerned that the memory access did not seem to respond to the WAIT fast enough. This timing acts as a reminder that the WAIT signal is asynchronous to the internal clocking and provides the delay for the absolute worst case timing.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Mastermind 7980 points

    Hi Bill,

    I would like to know what #14 and #28 are defined for.
    The maximum value of this timing is also 4E + 3ns, what is the difference the delay time(#11 and #25)?

    Best regards,
    H.U