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AM5716: PCIe EP questions

AnBer
Mastermind 29150 points
Part Number: AM5716

Team,

Could you please confirm that the below use case are supported in the AM57x PCIe when used as EP and by the associated Linux drivers too.

The system would like the below:
-AM57x CPU will be used just for the EP config and interrupt management.





Q: Can the AM57x (as PCIe EP) do DMA access (read/write) the RC RAM directly over PCIe (see green arrow)?
-Is it supported by the PCIe EP driver directly?

Q: Can the Host RC access (read/write) the different AM57x peripherals registers (like USB, Ethernet) over PCIe (see orange arrow)?
Q: According to the TRM SPRUHZ7G pg 6124 section 24.9.4.2, PCIe inbound read/write access is provided to the L3_MAIN, Can the peripherals on L4_PERx (see TRM page 377) be accessed via this mechanism through L3_MAIN?

Q:Can the DMA controllers used for USB and Ethernet peripherals access the 256 MiB PCIe outbound address space (See TRM pg 6126 section 24.9.4.3.2)?

Q: Can there be some hang-up situation when the PCIe interface is interrupted on the RC or EP side? Is this automatically managed by the PCIe HW? Should this be handled in the RC and EP driver?

Q: Regarding PCIe Linux driver benchmarks and performance:
What does the "PCIe-ETH" performance test refer to? Is there a description on the test case?
http://processors.wiki.ti.com/index.php/Processor_SDK_Linux_Kernel_Performance_Guide#PCIe_DriverDo we have additional performance figures available?
I have seen the below post that mention some performance but it does not seem to be performed on each Linux driver release:
https://e2e.ti.com/support/arm/sitara_arm/f/791/p/591681/2174826

Thanks in advance,

Anthony

  • 0
    TI__Guru**** 393215 points
    The PCIe experts have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru 50170 points
    Hi, Anthony,

    1. EP DMA can be done if RC RAM is mapped, but DMA transfer on EP is not implemented in current release.
    2. It can for memory mapped registers and if those registered are mapped to PCIe outbound/inbound area.
    3. Same as 2 and need to be mapped to PCIe outbound/inbound area.
    4. DMA controller on RC can be used, but it will need to set up its own channel for PCIe. It is currently not implemented.
    5. I am not sure about this question. Do you mean is there any case the PCIe gets locked up due to malfunction on either RC or EP side? Could you elaborate a bit more?
    6. The PCIe-Eth numbers are the results from running iperf through PCIe Ethernet card. They are used more for regression purpose, not true benchmark because the performance bottleneck is at the GbE of the PCIe card. The e2e thread on the PCIe performance is through RTOS setup, not linux.

    Rex