BT.656 and CCDC

Zheng,

The 656 logic works by taking the sync code and generating an internal pulse for HD and a multi-line signal for the VD.

Whenever we receive the FF 00 00 FVH if the FVH field indicates a start of active vide we generate a active high pulse that is at the same time as the FVH data. This occurs before the polarity selection for the pulse so for 656 data you should set the HD polarity to negative.

If the FVH code marks it as the start of the blanking period at the end of the frame we take the VD high and it remains high until we get the FVH code marking the first active line for the next frame. So again for this case you should set the VD polarity to negative so that the first pixel of the first line seen internally is the first active pixel.

Now to your specific questions.

First is on the edge of HD and VD.

In this graph internal HD and VD are negative during SAV, so upon entering or exiting SAV there are both first a falling edge and then a rising edge. Since many of the registers, including SDRAM address register SDR_ADDR, are all “latched by VD” according to the specification (p.133, table 67), so does these “latched by VD” registers latched at the rising or falling edge of the internal VD here?

The latched by VD can be either on a rising or falling edge based on the VD polarity which is controlled by a register bit. Internally we generate a pulse when the edge specifed has occured an pass this through the rest of the data pipeline to latch registers when this new frame starts.

How long is the latency? The forgoing question is probably trivial since as long as the data is latched after the period of VD, it doesn’t matter whether on the falling or rising end this happens. But after the register is latched, specifically, taking the particular case of SDR_ADDR, will the frame immediately following this preceding VD be written to a new address specified by the updated SDR_ADDR? It is just a question on the latency so that how long the new setting will start to take effect.

As stated above the register will latch when the new frame pulse reaches that processing block. We stream the different processing blocks together so the exact latency will vary but the first pixel of a new frame will always go out to the SDR_ADDR that is in the register when the new frame pulse arrives to the sdram processing module.

Second is on the length of HD and VD.

In this graph the internal HD and VD have equal length as SAV, which, according to BT.656 standard, is a four bytes sequence FF 00 00 XY. Therefore, does the bottom of HD and VD also last for the time equaling the transferring time for four bytes?

 As I stated above the HD is a single pulse and the VD will change to align with the XY in your byte sequence above.

Third is on “internal delay”.

In this graph there is an internal delay between “Data in” and “Internal data”. For

1.      “Data in”, is this the data from image sensor or encoder?

2.      “Internal data”: According to p.14, Fig.1” Video Processing Subsystem (VPSS) Block Diagram”, and p.19, Fig.2 “VPFE block diagram”, and the first section in p.15 that CCDC “provide an interface to image sensors and digital video sources”, do does “internal data” here mean the output of CCDC, which goes to VPI (video port interface) in Fig.1which are then supplied to either resize, previewer, H3A or histogram?

 I am not sure where this diagram came from but I think the intent was to try and show that the internal pulses are realigned so that if the polarity is set correctly the pulse is aligned with the first pixel of active data.

Fourth is on SPH.

According to p.129, Table 61, SPH:

“Sets pixel clock position at which data output to SDRAM begins, measured from the start of HD.”

But contrary to this description, in this graph, the left end of the SPH interval is aligned with the rising end of HD, which is its end rather than start. Why there is such a difference here? From where should SPH be measured?

SPH is measured from the internal pulse. So it depends on the polarity of the HD and VD. All transitions for 656 mode occur at the same time as the FVH data.

I hope this has answered your questions.

Regards,

David Smith

Dear David,

David Smith said:

Whenever we receive the FF 00 00 FVH if the FVH field indicates a start of active vide we generate a active high pulse that is at the same time as the FVH data. This occurs before the polarity selection for the pulse so for 656 data you should set the HD polarity to negative.

Please excuse me for my triviality here. How long is the "active high pulse" you are referring to? Does it become high at F0(elsewhere)0(SAV) (see BT.656 standard)? When does it become low? Does it become low at the beginning of the next SAV? Within the blanking period all SAVs are F1(during blanking)0(SAV) and F1(during blanking)1(EAV) and there is no way to know the end of the blanking period from these SAVs and EAVs until receiving the next F0(elsewhere)0(SAV), but here the hardware generate an "active high pulse"? From Fig.5 I think it looks like a "falling and rising" short pulse whose length is probably just one or two pixels.

I am understanding you correctly?

David Smith said:

If the FVH code marks it as the start of the blanking period at the end of the frame we take the VD high and it remains high until we get the FVH code marking the first active line for the next frame. So again for this case you should set the VD polarity to negative so that the first pixel of the first line seen internally is the first active pixel.

Do you mean when the hardware detect a F1(during blanking)0(SAV) VD is made immediately to high? If this is true what is the status of VD before that, during the active lines, including EAV of the last active line, and during the period between that last EAV and this F10? Is VD low during this period? But in Fig.5 VD seems to be high during this time.

Could you expand more on this?

I am still studying your remaining points and will do the homework before replying.

Sincerely,
Zheng

Zheng,

The HD pulse is for a single cycle at the same time as the FVH pixel. The VD is sampled every FVH period when H is 0 and takes the value of the V bit . In the figure you first referenced all the signals were inverted since it was showing the logic after the polarity switch. So if you have a standard 656 stream you get an HD high pulse for a single cycle on every SAV. You get VD high for every cycle of the blanking.

Regards,

David Smith