cycle accurate simulation of external memory

Using the dm6437 little endian simulator and modifying the simdm6437.cfg file to use L1/L2 as 100% SRAM, I have successfully produced a set of edma ping pong buffers that are chained together to accomplish input & output.  My test code basically triggers a transfer, which consists of moving about 8k from ddr2 to L1D SRAM, which is chained upon completion to another transfer that moves about 4k from a different L1D SRAM buffer to a different DDR2 location.  The transfers are a-b sync and all data movement is to consecutive locations with no sorting.  No other processing is done, this is just a data movement framework.

When I run this in an effort to judge my ddr2 throughput rate, I get only about 70MB/s transfer rate (moving about 1 MB takes over 9 million clocks).  The code spends 99.9+% of its time polling for completion of the edma transfers.  So I have to ask a few sanity check questions:

1) Does the simulator take into account tc optimization of transfer requests?

2) I noticed the simdm6437.cfg file contains a DDR_EMIF module.  I assume this means the simulator is at least attempting to model the ddr controller.  Within this block, I see lots of fields that I recognize as chip specific timing configurations, but I also see some unfamiliar entries.  Can someone explain the following fields & what I should be setting them to for ddr2 modeling?

sdram_enable 1; // SDRAM enable/disable control[ 1-enable, 0-disable ]

ddr_enable 1; // DDR enable/disable control[ 1-enable, 0-disable ]

ddr2_enable 1; // DDR2 enable/disable control[ 1-enable, 0-disable ]

system_bus_width 64; // System bus width in bits

narrow_mode 0; // Narrow mode enable/disable control

stat_fifo_depth 7; // Write statue FIFO depth

wr_fifo_depth 11; // Write data FIFO depth

cmd_fifo_depth 7; // Command FIFO depth

rreg_fifo_depth 2; // Register read FIFO depth

rsd_fifo_depth 17; // External memory read FIFO depth

rcmd_fifo_depth 22; // Read command FIFO depth