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Tool/software: TI-RTOS
Hello all,
I am trying to configure Vision SDK 3.03 DDR test example to run with 3GB of RAM on TDA2p. 2GB are connected to EMIF1 and 1GB is connected to EMIF2. Changes that I have made are:
- (Vision_PATH)/vision_sdk/links_fw/src/rtos/bios_app_common/tda2px/a15_0/a15_0.cfg (line 165. Mmu.setSecondLevelDescMeta(i, i, attrs2))
- (Vision_PATH)/vision_sdk/links_fw/src/rtos/bios_app_common/tda2px/ipu1_0/Ammu1_bios.cfg (line 207. entry.translatedAddress = 0xA0000000)
- (Vision_PATH)/vision_sdk/links_fw/src/rtos/bios_app_common/tda2px/ipu2/Ammu2_bios.cfg (line 207. entry.translatedAddress = 0xA0000000)
- (Vision_PATH)/vision_sdk/links_fw/src/rtos/bios_app_common/tda2px/eve_common/tlb_config_eve_common.c (line 100. #define SIZE_3G (0xC0000000U), line 134. instead of SIZE_1GB, set SIZE_3GB)
- (Vision_PATH)/vision_sdk/apps/configs/build_makeconfig.mk (line 106. $(ECHO) \# DDR_MEM=$(DDR_MEM) [options: DDR_MEM_128M DDR_MEM_512M DDR_MEM_1024M DDR_MEM_3G])
- (Vision_PATH)/vision_sdk/apps/configs/defaults.mk (line 16. DDR_MEM=DDR_MEM_3G)
- (Vision_PATH)/vision_sdk/apps/configs/tda2px_evm_bios_all/cfg.mk (DDR_MEM=DDR_MEM_3G)
- (Vision_PATH)/vision_sdk/build/rtos/makerules/component.mk (after ifeq($(DDR_MEM),DDR_MEM_512MB
vision_sdk_CFLAGS += -DTDA2XX_512MB_DDR
endif
added ifeq ($(DDR_MEM),DDR_MEM_3G)
vision_sdk_CFLAGS += -DTDA2XX_3GB_DDR
endif
-(Vision_PATH)/vision_sdk/links_fw/src/rtos/utils_common/include/utils_mem_cfg.h (after #ifdef TDA2XX_512MB_DDR block added
#ifdef TDA2XX_3GB_DDR
#ifdef ECC_FFI_INCLUDE
#define UTILS_MEM_HEAP_DDR_CACHED_SIZE (309*1024*1024)
#else
#ifdef OPENCL_INCLUDE
#define UTILS_MEM_HEAP_DDR_CACHED_SIZE (249*1024*1024)
#else
#define UTILS_MEM_HEAP_DDR_CACHED_SIZE (700*1024*1024)
#endif
#endif
#endif
After all this, I made mem_segment_definition_3gb_bios.xs file based on mem_segment_definition_bios.xs file and placed it in (Vision_PATH)/vision_sdk/apps/build/tda2px/. Changes that I made were DDR3_SIZE = (1024+2048)*MB and DDR3_BASE_SIZE_0 = 1008*MB.
Later, I included mem_segment_definition_3gb_bios.xs in files config_a15.bld, config_arp32.bld, config_c66.bld, config_m4.bld. Add
if (platformMem == "DDR_MEM_3G")
{
var MemSegDefine = xdc.loadCapsule("mem_segment_definition_1_5gb_bios.xs");
}
after
if (platformMem == "DDR_MEM_512M")
{
var MemSegDefine = xdc.loadCapsule("mem_segment_definition_bios.xs");
}
After that, I set the SBL like this:
-(Vision_PATH)/vision_sdk/build/rtos/makerules (line 127. PDK_SBL_BUILD_OPTIONS = $(PDK_BUILD_OPTIONS) EMIFMODE=DUAL_EMIF_3GB)
-(Vision_PATH)/ti_components/drivers/pdk_01_09_00_17/packages/ti/boot/sbl_auto/sbl_lib/src/tda2xx/sbl_lib_config_tda2xx.h (line 63. TDA2XX_EMIF_MODE is set to (SBLLIB_DUAL_EMIF_3GB))
-(Vision_PATH)/ti_components/drivers/pdk_01_09_00_17/packages/ti/boot/sbl_auto/sbl_utils/src/tda2xx/sbl_utils_tda2px_ddr_config.c after #if (TDA2XX_EMIF_MODE == SBLLIB_SINGLE_EMIF_512MB) block I put
#if (TDA2XX_EMIF_MODE == SBLLIB_DUAL_EMIF_3GB)
{
SBLLibPrintf(SBLLIB_TRACE_LEVEL_DEBUG,
" Two EMIFs in non interleaved mode (3GB total)\n");
/* MA_LISA_MAP_i */
HW_WR_REG32(SOC_MA_MPU_CONF_REGS_BASE + LISA_MAP_0, 0x80700100U);
HW_WR_REG32(SOC_MA_MPU_CONF_REGS_BASE + LISA_MAP_1, 0xC0600200U);
/* DMM_LISA_MAP_i */
HW_WR_REG32(SOC_DMM_CONF_REGS_BASE + LISA_MAP_0, 0x80700100U);
HW_WR_REG32(SOC_DMM_CONF_REGS_BASE + LISA_MAP_1, 0xC0600100U);
}
#endif.
I changed a little the DDR test, in main.c defined DDR_SIZE_EMIF1 to 0x7FFFFFFF, and DDR_SIZE_EMIF2 to 0x3FFFFFFF, also I defined EMIF1_DDR_BASE_ADDRESS to 0x80000000 and EMIF2_DDR_BASE_ADDRESS
to 0xC0000000. The problem is when I run the test, and try to run full memory read/write test, the message I get on terminal is Size of DDR is 0x0. Do you maybe know why that happens?
Best regards,
Bosko
