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TMS320C6678 : About EDMA3 operation... DDR to DDR

kitae Kim
Prodigy 100 points
Part Number: TMS320C6678

Hello?
Thanks for your help in advance.

I refer to the ping-pong example in the following location.
C: \ ti \ pdk_c667x_2_0_7 \ packages \ ti \ csl \ example \ edma \ edma_test.c
We converted the local address to a global address and confirmed the operation.
(Used in core 2)
However, if you test by setting srcAddr, dstAddr as DDR area (example: src = 0x90000000, dst = 0x90001000), you can not copy data.

Transmission is completed through regionInter. But it does not copy.

I do not know what I'm missing.
(Note that DDR regions have allocated independent regions for each core (via the make platform))

Waiting for help.
Thank you.

  • 0
    TI__Guru**** 161600 points
    Hi,

    Are you using TMDSEVM6678?
    I will run the example on this board and let you know the results.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Prodigy 100 points
    Thank you for your reply.
    I use a custom board.

    I found a solution in the EDMA3_LLD example and the TMS320C66x DSP Cache documentation.
    In the LLD example, you must set the cache when using DDR memory for src and dst. This allows DDR to DDR EDMA data copying.

    Due to my lack of understanding, there is one question.
    Do I have to use cache when using DDR memory? If so, why?
    If it is your time, please answer.

    Thank you.
  • 0 in reply to kitae Kim
    TI__Guru**** 161600 points
    Hi,

    If you use the internal DMA of DSP corepack you should use cache, see Internal Direct Memory Access (IDMA) Controller form the C66x CorePack User Guide: www.ti.com/.../sprugw0c.pdf

    When using EDMA I don't think it is necessary to use cache. You can disable caching for the ddr regions that you use and perform DDR to DDR EDMA data copying without cache: e2e.ti.com/.../344753

    Best Regards,
    Yordan