TMS320C6678: DDR pins connection about TMS320C6678 when not using DDR

To Team, Please answer this question. It is taking 10 days 

Daisuke,

There is the following application note, but I didn't see anything specifically addressing this question in section 6.1.1. Will forward this question internally. 

https://www.ti.com/lit/pdf/sprabi1

Regards,

Kevin

Kevin, Thank you for your replay, Customer need to fix the circuit Design ASAP and need to clear this pending items. Could you answer it within today/tomorrow? 

The data manual states if clock is unused it must be held at static state by pulling N leg to GND and P leg to VDD (for that specific IO).  Yes all power rails are required to have proper voltage and sequence applied.

Robert, Thanls for answer. I design as below:

1. Can DDR pins be open(No Connect)?

 open except to clock pins ans power pins.

2. Can DDRCLK(66MHz) pin be open?

 pulling N leg to GND and P leg to VDD

3. Must DVDD15 and AVDDA2 be supplying power?

 supplying power and applying power sequence

I recommended also connecting unused DQS/DQSn pins to pullup/down resistors (similar to DDRCLK).  Other DDR pins can be left open.