Other Parts Discussed in Thread: CDCM9102,
Tool/software: Linux
Hello, experts. On my custom board CPU and FPGA are connected via PCI-E x2 gen1 mode. ARM is RC, FPGA is EP and is powered on before RC. I use 125 MHz REFCLK generator. The link is very unstable: one time i see "link never came up" when board starts up, next time link up, but lspci doesn't show FPGA device revision correctly (I see 0xFF). Is it software or hardware problem? I checked schematics and pcb: pci reset gpio is functional and PMIC voltage outputs are okay, differential pairs too. I also used same FPGA IP-block with 125 MHz in other board.
So does AM5728 PCI-E core support 125 MHz or 100 MHz is maximum (I noticed CDCM9102 generator in EVM schematic) ?
SDK05.00.00.15, Design is based on AM5728 GP EVM.
