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AM5718: How the data bus should be connected to the DDR memory

Yousef
Prodigy 10 points
Part Number: AM5718

Hi,

I have a question regarding the sitara processor XAM5718ABCXE and how it should be connected to DDR3L memory.
The picture below from the reference design shows how data bus is connected to the DDR memory.
I am a bit confused why for instance DDR_D4 is connected to DQ2 and not to DQ4!
I am using DDR3L in my design and wondering if it should be connected in the same sequence?