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CCS/TMS320C6455: TMS320C6455 can't boot when code is specific size

Part Number: TMS320C6455

Tool/software: Code Composer Studio

Hello all,

I'm working on a project where I'm adding a new feature to a board which runs a tms320c6455 DSP. The DSP is loaded through an HPI interface from a PowerPC chip, and it has 64MB of DDR2 attached.

The tools I'm using are:

Code Composer Studio 3.3.81.6

BIOS version 5.31.09

Before I started the project, the software was working just fine. I could run the code on the debugger. I could flash the board with an image and the PowerPC chip would load the code to the DSP and it would run just fine. Fast forward several months to the end of the project, and I'm putting the finishing touches on the new feature. I add a few lines of code and all of a sudden the DSP won't boot from the HPI interface anymore.

Starting from the code that doesn't run, here are the things I've tried so far to fix the issue:

1. Remove a few lines of code from IRAM. - This makes the issue go away.

2. Add a few lines of code to IRAM. - This makes the issue go away.

3. Remove a few lines of code from DDR2 RAM - This makes the issue go away.

4. Add a few lines of code to DDR2 RAM. - This makes the issue go away.

5. Run the code on a debugger with CCS. - This makes the issue go away.

6. Replace the code I added which caused the issue with function calls which just basically do a "nop" but keep the code size the same. - This does not fix the issue.

7. Remove all code added in this project, replacing it with function calls which basically do a "nop" but keep the same code size. - This does not fix the issue.

8. Remove all code from executing on the DSP except for a heartbeating thread which sends an IP packet periodically (too see if the DSP is alive) and the BIOS and replacing it with function calls which basically do a "nop" but keep the same code size - This does not fix the issue.

Additionally, I've checked the boot code to see how the PLLs and EMIF are set up. They match the GEL file setup for the debugger exactly. It's very currious that the code doesn't have the issue on the debugger, but when I flash the code to the board it doesn't work. Also, since I stripped out almost all of the application code, I feel like this can't be a logic issue in my software. I've spent quite a bit of time pouring over map files where I compare builds that run correctly with builds that don't, and the biggest takeaway I've seen with this is how much the compiler moves things around with even the smallest code change. Additionally, I find it odd that I can make the issue go away if I use more or less of the IRAM or more or less of the DDR2. When I experience the failure to boot, my IRAM usage is 0x1b9fb9 and the DDR2 usage is 0xb89aa0. (from the map file.)

My guess is that something is not lined up on an appropriate boundary somewhere depending on the code size, but I have no idea how to find out what or where it is.

Any recomendations or suggestions are greatly appreciated.

  • Hi Brian,

    It looks like HPI can only make 32-bit aligned accesses, so your code sections need to be 32-bit aligned. See section 3.3.4 of the Bootloader User's Guide for the TMS320C645x/C647x (Rev. G)

    I believe you can accomplish this by doing something like this in your linker .cmd file:

    .text          >  DDR2 ALIGN(4)

    Let us know how it goes. 
  • Thank you for your response. I have verified that the host processor is loading 32 bits at a time. I also modified the linker command file as you suggested to add the ALIGN(4). I tried this for the text section and the HighMemText (DDR2) section. Neither of these changes resulted in a change in the map file and they did not fix the problem. Adding the changes did create the following warnings during link:
    >> warning: Output section ".text"'s user specified run alignment of 4 is
                overridden to be 32 by the required alignment of the input section
                in "./Debug/xxx.obj"

    >> warning: Output section "HighMemText"'s user specified run alignment of 4 is
                overridden to be 32 by the required alignment of the input section
                in "./Debug/yyy.obj"
       
    I inspected the source code for those files, and I could not determine why they caused 32 byte alignment. My guess is that it has something to do with the generated bios config script, but I have not identified anything in it which would cause 32 byte alignment.

    Any additional suggestions are appreciated.

  • Since the last post I have verifed that the DSP is getting the correct data by reading back everything over the HPI interface after programming and verifying it is correct. I have also tried adjusting the linker command file to change which part of memory is being used. This did not solve the issue.

    Help is appreciated. This issue is jeopardizing our software delivery.

  • Brian,

    Can you check the document that describes creation of boot image for HPI boot here:
    www.ti.com/.../sprab60.pdf

    The boot image requires each of the section size to be multiple of 4 bytes. Is it possible that without the additional IRAM or DDR2 , the resulting image contains a section load that is not multiple of 4 bytes. If the section size is not a multiple of 4 bytes, padding will be added to the end of the raw data. The padding does not need to be copied to DSP memory. Refer to the note in section 3.1

    Regards,
    Rahul
  • Thanks for the help. The documentation provided helped me find an obscure bug in our HPI loading code which was dependent on the code size.