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AM3352: DDR3 Reset Line Control at Bootloader Phase

John Chiu
Intellectual 260 points
Part Number: AM3352

Hi TI support,

On boot up but prior to OS (QNX is this case) loading, I have a requirement to ensure DDR3 contents (memory locations) are returned to a "blank" state - random, zeroes, or ones.  Is it possible to gain access to DDR3 reset line during bootloader phase?

The desire behavior is to hold DDR3 in reset and/or  disable any refresh cycle from occurring for 100ms prior to normal kernel code load sequence.  Please advise if code executing in on-chip SRAM can access Sitara's DDR3 controller register to toggle the DDR3 reset line.

Thanks,

John

  • 0
    TI__Guru**** 393215 points
    Hi,

    QNX is not supported by TI, however the Linux MLO/SPL is executed from internal SRAM and it does configure the AM335x EMIF, so that U-boot can be loaded in it. The Linux SDK is available here: www.ti.com/.../PROCESSOR-SDK-AM335X
  • 0 in reply to Biser Gatchev-XID
    Intellectual 260 points
    What register in Sitara is used to set/reset DDR reset? Where in MLO/SPL control the DDR reset line?
  • 0 in reply to John Chiu
    TI__Guru* 85820 points

    John, the DDR3 RESET signal does not guarantee anything about clearing or randomizing the data in the memory.  All it does is reset internal state machines and logic inside the memory.    If you want to guarantee data is completely erased or random, you would have to fill the memory, or ensure to cut power to the memory for quite some time.  A lot of it will depend on temperature and leakage currents.  Also, depending on how strong the cells are, some memory locations may be able to retain their value well beyond the refresh interval.  

    If you are coming from a powered off state, the memory will be random after initialization. But if you are rebooting from a powered state, you would have to fill the memory, or somehow cut the power to it before reinitializing.  The DDR_RESET signal is controlled by the DDR controller during initialization and ensures proper timing based on the DDR3 JEDEC specification.   

    Regards,

    James

  • 0 in reply to JJD
    Intellectual 260 points
    Hi James,

    Understood on the limitation of relying on holding DDR reset line active to discharge DRAM storage caps.

    Is there a method for user code executing in SRAM to control the DRAM reset line? Is the reset line solely controlled by Sitara's DDR controller ? This would imply user code can not gain control of the reset line to the DDR memory?

    Thanks,

    John
  • 0 in reply to John Chiu
    TI__Guru* 85820 points
    John, i don't understand what code would do with the RESET signal to the DRAM even if it could have control of it? What are you trying to accomplish by just toggling the RESET signal?
    The timing sequence involving the DDR_RESET and other signals during DRAM initialization has to follow a strict timing requirements setup by the JEDEC spec. The DDR controller takes care of this.

    Regards,
    James
  • 0 in reply to JJD
    Intellectual 260 points

    James,

    Code executing in SRAM during bootloader phase ( say end of DDR controller initialization) would write to control register which in turn assert DDR reset line for x seconds.  At the end of x seconds, code will write to control register to release DDR reset line.  Holding reset line for x seconds would allow DRAM storage caps to discharge below noise floor.

    Rgds,

    John

  • 0 in reply to John Chiu
    Guru 92251 points

    John Chiu said:
    Code executing in SRAM during bootloader phase ( say end of DDR controller initialization) would write to control register which in turn assert DDR reset line for x seconds.

    I see can't any way for software to explicitly control the state of the DDR_RESETn pin. However, there is the reg_phy_rst_n bit in the DDR_PHY_CTRL_1 (and DDR_PHY_CTRL_1_SHDW) registers:

    If the bootloader sets the reg_phy_rst_n bit for X seconds, clears the reg_phy_rst_n bit and then continues with DDR controller initialization maybe that will have the desired effect.

    From the AM335x Technical Reference Manual it is not clear if setting the reg_phy_rst_n bit asserts the DDR_RESETn pin.

  • 0 in reply to Chester Gillon
    TI__Guru* 85820 points
    John, after a power on reset, the RESET signal should be low until the DDR functional clock is enabled. I would just put your x second timeout before enabling the DDR functional clock. Do you need to perform the clearing of the DDR at any other time, or just on boot up?

    Chester, that bit just performs an internal reset of the DDR PHY.

    I think we can accomplish what you guys need, it just won't involve manually controlling the DDR_RESET signal.

    Regards,
    James
  • 0 in reply to JJD
    Intellectual 260 points

    James,

    We just need to clear DDR contents on power up.  What is recommend procedure to keep DDR functional block ( or clock) in disabled?  What registers we need to hit?

    Thx,

    John

  • 0 in reply to Chester Gillon
    Intellectual 260 points
    Hi Chester,

    Thanks for pointing out the control register to manipulate PHY macros. Will try this out.

    Thanks,

    John
  • 0 in reply to John Chiu
    TI__Guru* 85820 points
    John, EMIF functional clock is controlled by PRCM_CM_PER_EMIF_CLKCTRL register. This is enabled in MLO before all of the EMIF initialization occurs.

    Regards,
    James
  • 0 in reply to JJD
    Intellectual 260 points

    Thanks.

    -John