AM3352: DDR integration test

Denny%20Yang99373

Expert 3805 points

Part Number: AM3352

Hi team,

Customer use agilent scope to do the intergrated test (JEDEC) standard.

But failed at some spec like below:

The DDR read and write test is fine.

Do you have any comments about this test? How to improve this? thanks!

BR,
Denny

over 6 years ago

0 JJD over 6 years ago

TI__Guru* 80740 points

Denny, ensure the customer has followed all of the DDR routing guidelines in the AM3352 datasheet, section 7.7.2.3.

Also ensure they have performed the software leveling procedure found here if they are using fly-by topology: processors.wiki.ti.com/.../AM335x_DDR_PHY_register_configuration_for_DDR3_using_Software_Leveling

or if they are using T-topology, they should at least use the ratio seed spreadsheet to generate the proper delays in the PHY for their board

The Vih/Vil violations could be the results of an unstable VREF. Be sure they check VREF voltage, which has a 2% tolerance.

Regards,
james

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AM3352: DDR integration test