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TMS320C6657: TMS320C6657 Clock Design

Part Number: TMS320C6657
Other Parts Discussed in Thread: CDCE62005, CDCM61004

Hi.

I am trying to design a board using the TMS320C6657.

I have a question about the clock.

On the evaluation board, the FPGA controls the clock by setting the CDCE62005.

But I do not want to use an FPGA.

So I try to design the clock using the CDCM61004.

MCMCLK and PCIECLK are not used.

I know that 250MHz meets the input clock frequency range of the TMS320C6657.

I would like to know if there is any problem with this design.

Thank you and regards.

Myeongsu

  • Hi Myeongsu,

    I am not familiar with the CDCM61004 device, in general this clocking scheme should work. Note that you need to comply with the datasheet recommendations, as well as follow the guidelines in Chapter 3 Clocking from the Hardware design guide for Keystone devices.

    Best Regards,
    Yordan