TMS320C6657: TMS320C6657 Clock Design

Hi.

I am trying to design a board using the TMS320C6657.

I have a question about the clock.

On the evaluation board, the FPGA controls the clock by setting the CDCE62005.

But I do not want to use an FPGA.

So I try to design the clock using the CDCM61004.

MCMCLK and PCIECLK are not used.

I know that 250MHz meets the input clock frequency range of the TMS320C6657.

I would like to know if there is any problem with this design.

Thank you and regards.

Myeongsu