AM3517, AM3715 in via channel array packages -- SYSTEM level PCB stackups in real world applications; is 4 copper layers realistic?

Good day,

I'd like to get some feedback and clarification concerning the practically necessary real world whole system PCB design rules and
PCB layer stackup suggested for the AM3517AZCNA and the AM3715CUS. 

There appears to be a significant discrepancy between what the AM3517AZCNA datasheet specifies for a minimum stackup and what the Wiki article about ZCN package routing specifies as follows.  I see that the datasheet in its current revision is newer than the Wiki article, and would generally also be considered more authoritative, however the Wiki article does make some fairly compelling if a bit vague claims to the contrary. 

`AM35x VCA PCB layout PCB Escape Routing for ZCN Package Keven Coates / Paul Eaves May 2010.' -- "With the ZCN package, a four layer PCB design is possible for most systems."
--versus--
Datasheet:  `AM3517, AM3505 SPRS550B – OCTOBER 2009 – REVISED JULY 2010' -- "6.4.2.1.3 PCB Stackup The minimum stackup required for routing the AM35x is a six layer stack as shown in Table 6-14. Additional layers may be added to the PCB stack up to accommodate other circuity or to reduce the size of the PCB footprint."

Likewise, there appears to be a significant discrepancy between what the AM3715CUS datasheet specifies for a minimum stackup and what the Wiki article about CUS package routing specifies as follows.  I see that the datasheet in its current revision is comparable in date with the Wiki article.  Normally I'd think that the datasheet would be considered more authoritative, however the Wiki article does make some fairly interesting hints that 4-layer stackups might work for this part/package too, though it is even more vague about that than in the case of the ZCN packaged AM35xx above.

`AM37x CUS Routing Guidelines' -- "ABSTRACT CUS package is designed with a new technology called Via ChannelTM array. This technology allows for easy routing of the device in two signal and two power layers using standard 20 mil diameter and 10 mil finished hole size via; it is cost and time effective."
---versus--
Datasheet: `AM3715, AM3703 SPRS616D – JUNE 2010 – REVISED OCTOBER 2010' -- "5.4.2.1.3 PCB Stackup The minimum stackup required for routing the AM37x is a six layer stack as shown in Table 5-14. Additional layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size of the PCB footprint."

In both cases it is clear from the Wiki articles that it is just possible to perform BGA escape routing successfully in the exemplified four layer stackup, and presumably that's accomplished with good power and signal integrity and EMC characteristics at full MHz operation (though such isn't explicitly stated).  However the wiki articles stop there and do not really address signal integrity or routing issues that would typically relate to real world system implementations with the ARM MCUs plus DDR DRAM, FLASH, High Speed USB, Ethernet, use of the video I/O and LCD interfaces, et. al.  The datasheet suggests that a *minimum* of 6 copper layers PCB stackup should be used, and does that in the context of talking about signal integrity of DRAM interfaced to the MCU. 

I understand that there are PCB cost, routing and signal integrity benefits of being able to easily escape route the particularly packaged ARMs on 4 layers even if additional copper layers are practically required and used for additional routing and power distribution and peripheral signal integrity benefits at a system level.  Specifically the provisioning of more relatively unbroken power plane layers for more supply voltages may be relevant when one has a design requiring mixed supply voltages such as these would.  Also I cen see how the type/speed/amount of DDR memory might affect the need for additional layers.

Of course I understand that the particular DFM and stackup parameters will also be application specific depending on the customer's exact design of peripherals, PCB size, speed of operation, et. al.  Nevertheless, the Wiki articles are suggestive to some degree that potentially the entire system might well be implemented "in real world systems" in a 4 layer stackup including DDR RAM,  HS USB, video, LCD, ethernet, et. al. in non-trivial, non-minimal designs with reasonable signal integrity and so forth.  Is this true in the real world for these parts, or in practice is it going to be very much easier / safer / more practical to follow the datasheet's advice and use 6+ layers?

How does the situation relate to the type + amount of DDRx DRAM, FLASH?  How does it relate to choice of operating MHz of the CPU and RAM/FLASH?

If many real world designs and customers are successfully and easily implementing the entire system with fairly well stocked (DDRx RAM,FLASH,peripherals in use) system implementations on 4 layer PCBs then that is a very attractive aspect for these parts and packages.  On the other hand if it is something that is "just barely possible" with a minimal system peripherals, and with low MHz operation and significant restrictions on the peripheral additions and operational performance modes then I'd rather have that advice ab initio and not spend a lot of time working on a 4-layer layout that will not have good capabilities / SI / expandability, and just use 6 layers if I'm going to use the parts.

Are there any entire non minimal reference designs available for inspection that have been done in 4 copper layers including many of the peripherals in full use at max. MHz, DDRx DRAM, HS USB, and so on?

I do appreciate the guidance of the Datasheet and the Wiki article since the suggestions for escape routing and stackup will be very useful in any case, I just don't want to "read between the lines" and assume too much is possible for system level layer conservation when maybe what is being implied is more that the routing is easier to do with lower cost trace/space/via design rules and not so much that you can save the copper layers at the system level looking beyond the BGA escape routing.

Thanks in advance!