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CCS/66AK2G12: About DDR3 data bus width change

user5968673
Intellectual 430 points
Part Number: 66AK2G12

Tool/software: Code Composer Studio

Dear Rahul,

Currently, We develop our product using 66AK2G12,

And debug the DSP and ARM via Jtag using CCS.But there are some issues. Please advice.

We made the following changes from EVM to DDR3.
　・The chip changed from 4(+1 for ECC) to 1 piece.
　・The data width changed from 8-bits to 16-bits.

So we set the NM of EMIF_SDCFG Register to DDR3 data bus width is the 2 = 16-bit bus width.
Are there any other register need to change for DDR3 bus width change?
(Are there any register need to change about MSMC registers and other registers?)

Best regards.

  • 0
    TI__Mastermind 46460 points

    User,

    All DDR implementations require customized hardware and software commissioning.  You will need to adjust more than just the NM register field.  Please refer to the KeyStone II DDR3 Interface Bring-Up Application Report (SPRACM0) available from the 66AK2G12 product page at the link below.

     

    There are other application reports and tools linked within this document that support this commissioning.  Please provide a report showing that the length matching rules have been met in the layout and a version of the REG_CALC spreadsheet with the values from the SDRAM datasheet.

    Tom

  • 0 in reply to Tom Johnson 16214
    TI__Mastermind 46460 points

    User,

    Do you have any additional questions at this time?  If not we can close this thread.  A new one can be opened if this one is locked.

    Tom