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In am335x, I used the rtlinux version of PSDK. I consulted Datasheet about the interrupt part and found that MPU_INTC.INTC_ILRm registercould set the interrupt priority. Could I modify the gpio interrupt priority through this register in the driver?If so, how to modify and which function interface to call?
Hi Chen,
Yes, this MPU_INTC.INTC_ILRm register could be used for interrupt priority settings. This register is handled in below linux kernel file:
linux-kernel/drivers/irqchip/irq-omap-intc.c
Please refer to below e2e threads for details:
https://e2e.ti.com/support/processors/f/791/t/646848
https://e2e.ti.com/support/processors/f/791/t/523690
https://e2e.ti.com/support/processors/f/791/t/651105
https://e2e.ti.com/support/processors/f/791/t/496264
Regards,
Pavel
96 GPIOINT0A GPIO 0 POINTRPEND1
97 GPIOINT0B GPIO 0 POINTRPEND2
dts:
gpio0: gpio@44e07000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio1";
clocks = <&dpll_core_m4_div2_ck>, <&gpio0_dbclk>;
clock-names = "fck", "dbclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x44e07000 0x1000>;
interrupts = <96>;
};
I use GPIO_0_19 and GPIO_0_07, and I want to set GPIO_0_19 interrupt priority higher or lower than GPIO_0_07.
Is GPIO0 interrupt priority NTC_ILR96?How can I change the interrupt priority ofGPIO_0_19 and GPIO_0_07 ?
INTC_ILR96 Register (offset = 280h) [reset = 0h]
root@am335x-evm:~# devmem2 0x48200000
/dev/mem opened.
Memory mapped at address 0xb6f08000.
Read at address 0x48200000 (0xb6f08000): 0x00000050
root@am335x-evm:~# devmem2 0x48200280
/dev/mem opened.
Memory mapped at address 0xb6f47000.
Read at address 0x48200280 (0xb6f47280): 0x00000000
root@am335x-evm:~#
Chen,
You need to configure gpio0_7 for GPIOINT0A, and gpio0_19 for GPIOINT0B.
gpio0_7 -> GPIO_IRQSTATUS_SET_0[7] INTLINE = 0x1 -> GPIOINT0A 96
gpio0_19 -> GPIO_IRQSTATUS_SET_1[19] INTLINE = 0x1 -> GPIOINT0B 97
Then you need to configure IRQ number 97 with higher priority than 96.
And gpio0 module in linux-kernel/arch/arm/boot/dts/am33xx.dtsi as below:
- interrupts = <96>;
+ interrupts = <96 97>;
+ interrupt-names = "gpioint0a", "gpioint0b";
};
You can explore how the two McASP0 interrupts are coded, 80 and 81.
Thus gpio0_7 IRQ priority is controlled by INTC_ILR_96, gpio0_19 IRQ priority is controlled by INTC_ILR_97
Regards,
Pavel