TDA4VM: About on-die capacitance on DDR supply net and simulation for LPDDR4

Hi,expert

I read from the document "Jacito 7 LPDDR4 board design and layout guidelines"  that on die capacitance information should be considered duriing ddr signal simulation.  But I learned from TI FAE that TDA4 has no on-die capacitance.  This makes me confused that if we should use the on die decoupling circuit value for simulation as below.

And the fact is there are on-die capacitance on DRAM side, and if we set no on-die decoupling value in simulation project for controller, the output  DQ waveform would have a big amplitute(about 3V) for controller driver.

Please suggest how to deal with the on die information for TDA4 and would it be correct if the on-die capacitance value is used in simulaiton? Thanks