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TDA4VM-Q1: TDA4VM and VL LPDDR4 SI simulation tool confirmation

Alan Liu
Prodigy 50 points
Part Number: TDA4VM-Q1
Other Parts Discussed in Thread: TDA4VM

Hi team,

   TI requires that we should use 3d-EM solver in the document of "Jacinto7 Reference PCB Designs and Simulations v1.1". TI think it is critical for LPDDR4 design, but no mention any substantial data to illustrate why only 3D-EM solver is OK for LPDDR4 simulation. 

   we have reached more than two simulation service providers, and their comments are like these:1)for LPDDR4 ,they use 2D or 2.5D em solver for all the simualtion projects. and there is no problem report. 2) 2D or 2.5D EM solver is the most popular simulation tool for LPDDR4 SI simualtion. 3)it is difficult for them to do whole 3D simulation. only part of the circuit such as vias can be supported for 3D simualtion. 

   we have checked with micron, micron is using siwave/hspice for LPDDR4 simualtion. they are also 2D or 2.5D em solver. 

   so, there are two issues need TI help to check: 1) have TI checked the simulation efficacy difference between 2D and 3D EM solver? have TI checked if 2D or 2.5D tool is ok enough for TDA4 SI simulation? is there any comparing research data underlieing the conclusion that 3D-em solver is critical for LPDDR4? 2) please help to provide the TDA4 VM and VL LPDDR4 simulation report for their demo, and the test/verification data.

  • +1
    TI__Mastermind 47500 points

    3D EM solvers need more time and resources to extract models but are more accurate than 2.5D solvers like SIwave. We strongly recommend using 3D solvers for model extraction for high speed interfaces like LPDDR4 and SerDes. In particular, 3D solvers are better suited to model the crosstalk between vias, via impedance, and the effect of plane cutouts in the layout.

    If customer chooses to use a 2.5D solver to generate models, be aware of the simulation inaccuracies and add sufficient margin before completing their design. The following is for TDA4VM Example Layout/PCB Model. The 2.5D-3D differences will likely vary from one layout/stack-up to another.

    Sample TDA4VM data:

    Byte Sim Model Total EW Margin (ps) Total EH Margin (mV)
    Lane0 2.5D PCB Model 43.52 114.12
    Lane0 3D PCB Model 17.52 47.72
    Lane1 2.5D PCB Model 30.24 76.72
    Lane1 3D PCB Model 24.24 71.72

    If the customer wants to reduce model extraction time, they should extract the models in both (2.5D and 3D) tools, run DDR sims with them, and check the differences. In subsequent extractions (layout iterations), they can use the 2.5D tool but use adequate margin to compensate for tool inaccuracies.

    Finally, this is not our recommendation and we strongly urge using 3D tools for PCB model extractions.