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TDA4VM-Q1: Wolong preject TDA4VL LPDDR4 simulation LPDDR4_DQ17 crosstalk confirmation

Alan Liu
Prodigy 50 points
Part Number: TDA4VM-Q1
Other Parts Discussed in Thread: TDA4VL

Hi team,

     we have accomplished the LPDDR4 simulation. it was done by hyperlynx. we find that the LPDDR4_DQ17 have the max crosstalk of 68mV.  all DDR routings are reused from TI reference design "PROC118E1_BRD.brd" per to TI requirement. we check the wolong design and "PROC118E1_BRD.brd" design and we find out that the LPDDR4_DQ17 routing may cause the LPDDR4_DQ17 high crosstalk problem. the attachment is the wolong roLPDDR4 SI Simulation Report_20221028_V3.01.pdf uting, the  "PROC118E1_BRD.brd" routing and the simulation report. please help to confirm the following issues. 1) is 68mv crosstalk suitable with TDA4 VL requirements? 2) "PROC118E1_BRD.brd" has the same routing , what is  the TDA4VL verification status? does the high crosstalk have any negative influence or is it OK per the the PROC118E1 testing and verification result?

  • 0
    TI__Mastermind 47560 points

    As stated in other thread, TI does not measure crosstalk specifically (stand-alone).  Crosstalk of the signal(s) is included as part of the overall JEDEC eye mask simulation.   I will refer to another resource to respond on the status of testing/verification of the PROC118 design.  Note the validation was/is likely not done on version E1 of the design, but a later version.  We can also confirm the EVM version used during validation.

  • 0 in reply to Robert Eschler
    Prodigy 50 points

    hi robert,

        tks much for the information. 

    1. i have checked the LPDDR4_DQ17 routing both in E1 and E3 design. it sounds like the same routing design. i will compare the whole ddr routing in E1 and E3 later. so, please help to provide the DDR testing/verification information of the PROC118 design. we may reach a rudimentary conclusion if there is any risk.

    2. is there any more action can i take to check this issue? if we ask the simulation engineer to channel sim LPDDR4_DQ17 in 3D-EM solver, does it will help us to check if it is OK? please help to provide some comments about it. 

    tks.

  • 0 in reply to Alan Liu
    Prodigy 50 points

    hi robert,

        we found that E3 and E1 have the same DDR routing design. please help to share the testing/verification information of the PROC118 design, and help to provide some suggestion comments about the LPDDR1_DQ17 further simulation action. tks.

  • 0 in reply to Robert Eschler
    Prodigy 50 points

    Hi robert,

       anything to update?

  • 0 in reply to Alan Liu
    TI__Mastermind 34690 points

    Hi,

    Which DDR sub-system are you simulating? DDRSS0 or DDRSS1?

    Regards,
    Kevin

  • 0 in reply to Kevin S
    TI__Mastermind 47560 points

    Note the bit in question is DQ17 of DDRSS0.  Below is TI's simulation results from the EVM for byte lane 2 (which includes DQ17).  Again - I do not have crosstalk specific information for DQ17, but rather the overall simulation results for Byte Lane 2.

    Test Total EW Margin (ps) Total EH Margin (mV) P-P VDDQ Noise (mV)
    DDR0 Byte2 Read at Pad 7.36 12.72 10.46
    DDR0 Byte2 Write at Pad 39.66 100.04 206.84

    Test Total EW Margin (ps) Total EH Margin (mV) Vix DQS Ratio (%)
    DDR0 Byte2 Write at Pin 49.96 60.96 13.29
  • 0 in reply to Robert Eschler
    Prodigy 50 points

    Robert and kevin,

       tks for the comments.

    1. the EVM Byte lane 2 simulation result sound good. is byte lane 2 performance the worst comparing to the other bytes simulation result?

    2. please help to share the status of testing/verification of the PROC118 design. 

    3.  is there any more action can i take to check this issue? if we ask the simulation engineer to channel sim LPDDR4_DQ17 in 3D-EM solver, does it will provide more help? please help to provide some comments about it.

  • 0 in reply to Alan Liu
    TI__Mastermind 47560 points

    Yes - for DDR0 Byte lane 2 is worst performance/smallest margin.