TDA4VM: Asynchronous MCAN2 Rx and Tx along with DL based vision app application

Pooja R1

Part Number: TDA4VM
Other Parts Discussed in Thread: SYSBIOS

Hello ,

1. Currently we are working on camera based dl demo application.Able to asynchronously perform using MCAN2 either transmission or reception of messages by triggering the appMcan2Init() in appInit() [basic_demos/app_tirtos/common/app_init.c]

2. Now Tx of messages is happening after every 33ms using Task_sleep()

//pseudo code of Tx

while(1){

Txtest();
Task_sleep(timePeriodInMilliSec);}

3. Rx is also receiving messages continuously.

//pseudo code of Rx

while(1){

Rxtest();}

4. Our final objective is to allow Tx to happen after every 33ms once dl demo application completes each frame (~33ms) and also continuously receive messages.

Kindly provide some guidance on this.

Thanks and Regards

Pooja Krishna

over 4 years ago

0 Brijesh Jadav over 4 years ago

TI__Guru**** 407715 points

Pooja,

One of the way is to use TIDL output as graph parameter and once you dequeue a frame from TIDL output, you could post message to send/receive CAN message..

Rgds,

Brijesh

0 Pooja R1 over 4 years ago in reply to Brijesh Jadav

Intellectual 790 points

Hi Brijesh,

1. As suggested, the above approach will be again synchronous to dl demo application.

2.Issue observed with that approach will be similar to the already existing data transfer iproblem we are currently facing (limited to less than 512 bytes (pass by value) )using appRemoteServiceRun().

3. Ultimately our goal is to pass reference of shared buffer from A72 dl demo application once to mcu2_1 core and it should keep read/write the buffer depending on Tx/Rx of CAN messages. So that both camera based application and CAN Tx happening at 33ms also same time CAN Rx running continuously.

4. Currently CAN Tx happening at 33ms also same time CAN Rx with single interrupt line ,ISR is hanging before starting the application itself. Either Tx works or independently Rx works along with application but not together.

Kindly suggest some guidance on this.

Regards

Pooja Krishna

0 Karan Saxena over 4 years ago in reply to Pooja R1

TI__Guru* 75663 points

Hi Pooja,

On 4. the ISR hangs - does that mean you go into the ISR and never return? Or is it an error interrupt event? Can you please elaborate?

There is a xds110 debugger on the EVM and I would suggest debugging using that to get more insights.

So to reiterate, you are able to run Tx only or Rx only along with the vision apps, the problem happens when you try to do a periodic 33ms Tx and an asynchronous Rx along with the vision app. (please confirm)

Please provide the source code so that I can give you more pointed reply.

Regards,

Karan

0 Pooja R1 over 4 years ago in reply to Karan Saxena

Intellectual 790 points

Hi Karan,

1. On 4. the ISR hangs - does that mean you go into the ISR and never return? Or is it an error interrupt event? Can you please elaborate?

--> Actually behavior of MCAN application is not constant.Sometimes it runs continuously without hang , very next time just upon re-run wont even transmit message.Sometimes gets hanged after sending some messages.

Due to non-constant behavior,unable to conclude exactly the hang situation (it does not post the handle from ISR).

2. So to reiterate, you are able to run Tx only or Rx only along with the vision apps, the problem happens when you try to do a periodic 33ms Tx and an asynchronous Rx along with the vision app. (please confirm)

--> Currently Tx is triggered asynchronously at 33 ms with dummy data along with vision apps application. Also Rx is also running continuously asynchronous with application.
Actually Tx needs to be triggered at 33ms and Rx continuously. As of now since I was not aware how to trigger at mentioned time delay, so in my experiment I was still running at 33ms both Tx and Rx.

Attached the source code for review as below:-

1778.app_mcan2.c

/*
 *   Copyright (c) Texas Instruments Incorporated 2016-2019
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

/**
 *  \file     app_mcan2.c
 *
 *  \brief    This file contains MCAN sample code.
 *
 *  \details  MCAN operational mode is set to Classic CAN.
 *
 */

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
#define TIMER_CALL

#include <stdint.h>
#include <stdio.h>
#include <ti/csl/csl_types.h>
#include <ti/csl/soc.h>
#include <ti/csl/hw_types.h>
#include <ti/csl/arch/csl_arch.h>
#include <ti/csl/csl_mcan.h>
#include <ti/drv/uart/UART.h>
#include <ti/drv/uart/UART_stdio.h>
#include <ti/osal/osal.h>
#include <ti/drv/gpio/GPIO.h>
#include <ti/drv/gpio/soc/GPIO_soc.h>
#include <ti/csl/csl_gpio.h>
#include <ti/board/board.h>
#include <ti/drv/i2c/I2C.h>
#if defined (SOC_J721E)
#include <ti/drv/sciclient/sciclient.h>
#endif
#include <utils/mcan/app_mcan2.h>
#include <utils/remote_service/include/app_remote_service.h>
#include <utils/console_io/include/app_log.h>

#include <ti/drv/ipc/ipc.h>
#include <ti/osal/SemaphoreP.h>
#include "app_CAN_reader.h"
#include "app_sciclient_helper.h"
#include <ti/sysbios/knl/Task.h>

#include <ti/board/src/j721e_evm/include/board_cfg.h>
#include <ti/board/src/j721e_evm/include/board_pinmux.h>
#include <ti/csl/soc/cslr_soc_ctrl_mmr.h>
#ifdef TIMER_CALL
#include <ti/sysbios/timers/dmtimer/Timer.h>
#include <ti/osal/TimerP.h>
#include <ti/drv/uart/UART_stdio.h>
#include <ti/drv/uart/UART.h>

Timer_Handle timerHandle;

static uint32_t gMcanTask = 1U;
void (*fp_taskFxn)();
volatile uint32_t debugVar = 1U;
uint32_t numTimerTaskHit = 0;
#endif
/* ========================================================================== */
/*                                Macros                                      */
/* ========================================================================== */
#if defined (SOC_AM65XX)
#define APP_ENABLE_UART_PRINT                    (1U)
#elif defined (SOC_J721E)
#define APP_ENABLE_UART_PRINT                    (1U)
#endif

#define APP_MCAN_STD_ID_FILT_START_ADDR          (0U)
#define APP_MCAN_STD_ID_FILTER_NUM               (1U)
#define APP_MCAN_EXT_ID_FILT_START_ADDR          (48U)
#define APP_MCAN_EXT_ID_FILTER_NUM               (1U)
#define APP_MCAN_TX_EVENT_START_ADDR             (100U)
#define APP_MCAN_TX_EVENT_SIZE                   (5U)
#define APP_MCAN_TX_BUFF_START_ADDR              (148U)
#define APP_MCAN_TX_BUFF_SIZE                    (5U)
#define APP_MCAN_TX_FIFO_SIZE                    (5U)
#define APP_MCAN_FIFO_0_START_ADDR               (548U)
#define APP_MCAN_FIFO_0_NUM                      (5U)
#define APP_MCAN_FIFO_1_START_ADDR               (748U)
#define APP_MCAN_FIFO_1_NUM                      (5U)
#define APP_MCAN_RX_BUFF_START_ADDR              (948U)

#define APP_MCAN_EXT_ID_AND_MASK                 (0x1FFFFFFFU)

#define APP_MCU_MCAN_0_INT0                                   (0U)
#define APP_MCU_MCAN_0_INT1                                   (1U)
#define APP_MCU_MCAN_0_TS_INT                                 (4U)
#define APP_MCU_MCAN_1_INT0                                   (2U)
#define APP_MCU_MCAN_1_INT1                                   (3U)
#define APP_MCU_MCAN_1_TS_INT                                 (5U)

#define I2C_BUS_NUM                     (0)
#define TCA6424_SLAVE_ADDR              ((uint8_t) 0x23U)

#define TCA6424_CMD_AUTO_INC            ((uint8_t) 0x80U)

#if defined (SOC_J721E)
#if defined (BUILD_MCU1_0)
#define APP_MAIN_MCAN_2_INT0                (CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0)
#define APP_MAIN_MCAN_2_INT1                (CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_1)
#define APP_MAIN_MCAN_2_TS_INT              (CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_2)
#else
#define APP_MAIN_MCAN_0_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN0_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_0_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN0_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_0_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_2_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN2_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_2_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN2_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_2_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN2_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_4_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN4_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_4_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN4_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_4_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN4_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_5_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN5_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_5_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN5_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_5_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN5_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_6_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN6_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_6_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN6_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_6_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN6_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_7_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN7_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_7_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN7_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_7_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN7_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_9_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN9_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_9_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN9_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_9_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN9_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_11_INT0               (CSLR_R5FSS1_CORE0_INTR_MCAN11_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_11_INT1               (CSLR_R5FSS1_CORE0_INTR_MCAN11_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_11_TS_INT             (CSLR_R5FSS1_CORE0_INTR_MCAN11_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#endif
#endif

/* Print buffer character limit for prints- UART or CCS Console */
#define APP_PRINT_BUFFER_SIZE                       (4000)
#if defined (SOC_AM65XX)
/* Port and pin number mask for GPIO Load pin.
   Bits 7-0: Pin number  and Bits 15-8: Port number */
#define AM65XX_IDK_GPIO_CAN0_STB_PIN    (0x012F)
#define AM65XX_IDK_GPIO_CAN1_STB_PIN    (0x0143)
#endif
#if defined (SOC_J721E)
#define J721E_GPIO_GESI_CAN_STB_PIN     (0x003C)
#define J721E_GPIO_MAIN_MCAN2_STB_PIN   (0x007F)
#endif
/*****************************/
/*****************************/
#define TX_CODE 0
#define RX_CODE 0
#define TX_RX_CODE 1

volatile uint32_t gMcanIsrIntr1Status;
/*****************************/
/*****************************/
/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */
#define APP_USE_CAN
#if defined (APP_USE_CAN)
static pinmuxPerCfg_t gMcan2PinCfg[] =
{
    /* MyMCAN2 -> MCAN2_RX -> AC2 */
    {
        PIN_UART0_CTSN, PIN_MODE(3) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCAN2 -> MCAN2_TX -> AB1 */
    {
        PIN_UART0_RTSN, PIN_MODE(3) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gI2c0PinCfg[] =
{
    /* MyI2C0 -> I2C0_SCL -> AC5 */
    {
        PIN_I2C0_SCL, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    /* MyI2C0 -> I2C0_SDA -> AA5 */
    {
        PIN_I2C0_SDA, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gGpio0PinCfg[] =
{
    /* MyGPIO0 -> GPIO0_127 -> AC4 */
    {
        PIN_UART1_CTSN, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gMcanPinCfg[] =
{
    {0, TRUE, gMcan2PinCfg},
    {1, TRUE, gI2c0PinCfg},
    {2, TRUE, gGpio0PinCfg},
    {PINMUX_END}
};
#endif

static pinmuxBoardCfg_t gCockpitDemoPinmuxDataInfo[] =
{
#if defined (APP_USE_CAN)
    {1, gMcanPinCfg},
#endif
    {PINMUX_END}
};

uint32_t          gMcanAppdataSize[16] =
{0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
volatile uint32_t gMcanIsrIntr0Flag = 1U;
//volatile uint32_t gMcanIsrIntr1Flag = 1U;
SemaphoreP_Handle RxgSyncSem;
SemaphoreP_Handle TxgSyncSem;
MCAN_ECCErrStatus gMcaneccErr;
#define APP_MCAN2_BASEADDR                       (CSL_MCAN2_MSGMEM_RAM_BASE)
uint32_t gMcanModAddr = APP_MCAN2_BASEADDR;

MCAN_TxBufElement          txMsg;
MCAN_RxBufElement    rxMsg;
MCAN_MsgRAMConfigParams    msgRAMConfigParams;
MCAN_ConfigParams          configParams;

const uint32_t mcan2TxMsgId[] = {OBJ_MSG_ID1,OBJ_MSG_ID2,OBJ_MSG_ID3,OBJ_MSG_ID4,OBJ_MSG_ID5,OBJ_MSG_ID6,OBJ_MSG_ID7,OBJ_MSG_ID8,OBJ_MSG_ID9,OBJ_MSG_ID10,OBJ_MSG_ID11,OBJ_MSG_ID12,OBJ_MSG_ID13,OBJ_MSG_ID14,OBJ_MSG_ID15,OBJ_MSG_ID16,OBJ_MSG_ID17,OBJ_MSG_ID18,OBJ_MSG_ID19,OBJ_MSG_ID20,\
                                 OBJ_MSG_ID21,OBJ_MSG_ID22,OBJ_MSG_ID23,OBJ_MSG_ID24,OBJ_MSG_ID25,OBJ_MSG_ID26,OBJ_MSG_ID27,OBJ_MSG_ID28,OBJ_MSG_ID29,OBJ_MSG_ID30,OBJ_MSG_ID31,OBJ_MSG_ID32,OBJ_MSG_ID33,OBJ_MSG_ID34,OBJ_MSG_ID35,OBJ_MSG_ID36,OBJ_MSG_ID37,OBJ_MSG_ID38,OBJ_MSG_ID39,\
                                 OBJ_MSG_ID40,OBJ_MSG_ID41
};



#if defined (SOC_J721E)
/* GPIO Driver board specific pin configuration structure */
GPIO_PinConfig gpioPinConfigs[] = {
    /* Output pin : CAN STB */
    J721E_GPIO_GESI_CAN_STB_PIN   | GPIO_CFG_OUTPUT,
    J721E_GPIO_MAIN_MCAN2_STB_PIN | GPIO_CFG_OUTPUT,
};
#endif

/* GPIO Driver call back functions */
GPIO_CallbackFxn gpioCallbackFunctions[] = {
    NULL
};

/* GPIO Driver configuration structure */
GPIO_v0_Config GPIO_v0_config = {
        gpioPinConfigs,
        gpioCallbackFunctions,
        sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
        sizeof(gpioCallbackFunctions) / sizeof(GPIO_CallbackFxn),
        0,
    };
/* ========================================================================== */
/*                 Internal Function Declarations                             */
/* ========================================================================== */

/**
 * \brief   This function will configure MCAN module
 *
 * \param   none.
 *
 * \retval  status      configuration status.
 */
static int32_t App_mcanConfig(void);
static void Rxtest();

int32_t appRemoteServiceMCAN2Handler(char *service_name, uint32_t cmd,
    void *prm, uint32_t prm_size, uint32_t flags);
/**
 * \brief   This function will configure X-BAR for MCAN interrupts
 *
 * \param   none.
 *
 * \retval  status      configuration status.
 */
static int32_t App_mcanXBarConfig(void);

/**
 * \brief   This is Interrupt Service Routine for MCAN interrupt 0.
 *
 * \param   none.
 *
 * \retval  none.
 */
static void App_mcanIntr0ISR(uintptr_t arg);
static void App_mcanIntr01ISR(uintptr_t arg);

/**
 * \brief   This is Interrupt Service Routine for MCAN interrupt 1.
 *
 * \param   none.
 *
 * \retval  none.
 */
static void App_mcanIntr1ISR(uintptr_t arg);

/**
 * \brief   This is Interrupt Service Routine for MCAN TimeStamp interrupt.
 *
 * \param   none.
 *
 * \retval  none.
 */
static void App_mcanTSIntrISR(uintptr_t arg);
/**
 * \brief   This API will load the register from ECC memory bank.
 *
 * \param   txMsg           message object to be transmitted.
 *
 * \return  None.
 */
static int32_t App_mcanRegisterInterrupt(uint32_t intNum, void f(uintptr_t));

/* ========================================================================== */
/*                          Function Definitions                              */
/* ========================================================================== */
#define TCA6424_CMD_AUTO_INC            ((uint8_t) 0x80U)

/* Input status register */
#define TCA6424_REG_INPUT0              ((UInt8) 0x00U)
#define TCA6424_REG_INPUT1              ((UInt8) 0x01U)
#define TCA6424_REG_INPUT2              ((UInt8) 0x02U)

/* Output register to change state of output BIT set to 1, output set HIGH */
#define TCA6424_REG_OUTPUT0             ((uint8_t) 0x04U)
#define TCA6424_REG_OUTPUT1             ((uint8_t) 0x05U)
#define TCA6424_REG_OUTPUT2             ((uint8_t) 0x06U)

/* Configuration register. BIT = '1' sets port to input, BIT = '0' sets
 * port to output */
#define TCA6424_REG_CONFIG0             ((uint8_t) 0x0CU)
#define TCA6424_REG_CONFIG1             ((uint8_t) 0x0DU)
#define TCA6424_REG_CONFIG2             ((uint8_t) 0x0EU)



void SetupI2CTransfer(I2C_Handle handle,  uint32_t slaveAddr,
                      uint8_t *writeData, uint32_t numWriteBytes,
                      uint8_t *readData,  uint32_t numReadBytes)
{
    bool status;
    I2C_Transaction i2cTransaction;

    I2C_transactionInit(&i2cTransaction);
    i2cTransaction.slaveAddress = slaveAddr;
    i2cTransaction.writeBuf = (uint8_t *)&writeData[0];
    i2cTransaction.writeCount = numWriteBytes;
    i2cTransaction.readBuf = (uint8_t *)&readData[0];
    i2cTransaction.readCount = numReadBytes;
    status = I2C_transfer(handle, &i2cTransaction);
    if(FALSE == status)
    {
        UART_printf("\n Data Transfer failed. \n");
    }
}

void padConfig_prcmEnable()
{
    /* UART Init */
    Board_initCfg   boardCfg;
    Board_STATUS    boardStatus;

#if defined (SOC_J721E)
    I2C_Params      i2cParams;
    I2C_Handle      handle = NULL;
    uint8_t         dataToSlave[4];
#endif

    boardCfg = BOARD_INIT_MODULE_CLOCK |
               BOARD_INIT_PINMUX_CONFIG;
#if (APP_ENABLE_UART_PRINT == 1)
    boardCfg |= BOARD_INIT_UART_STDIO;
#endif
    boardStatus = Board_init(boardCfg);
    if (boardStatus != BOARD_SOK)
    {
        UART_printf("[Error] Board init failed!!\n");
    }

    /* Pin mux for CAN STB used in GESI board */
    *(volatile unsigned int *)(0x0011c0f4) = 0x20007;
    /* Pinmux for MAIN_MCAN4 */
    *(volatile unsigned int *)(0x0011c020) = 0x60006;
    *(volatile unsigned int *)(0x0011c024) = 0x60006;
    /* Pinmux for MAIN_MCAN5 */
    *(volatile unsigned int *)(0x0011c04c) = 0x60006;
    *(volatile unsigned int *)(0x0011c050) = 0x60006;
    /* Pinmux for MAIN_MCAN6 */
    *(volatile unsigned int *)(0x0011c054) = 0x60006;
    *(volatile unsigned int *)(0x0011c06C) = 0x60006;
    /* Pinmux for MAIN_MCAN7 */
    *(volatile unsigned int *)(0x0011c074) = 0x60006;
    *(volatile unsigned int *)(0x0011c078) = 0x60006;
    /* Pinmux for MAIN_MCAN9 */
    *(volatile unsigned int *)(0x0011c0cc) = 0x60006;
    *(volatile unsigned int *)(0x0011c0d0) = 0x60006;
    /* Pinmux for MAIN_MCAN11 */
    *(volatile unsigned int *)(0x0011c11c) = 0x60006;
    *(volatile unsigned int *)(0x0011c120) = 0x60006;

    /* GPIO initialization */
    GPIO_init();

    /* Enable CAN transceivers by setting the STB pins */
#if defined (SOC_AM65XX)
    GPIO_write(0, GPIO_PIN_HIGH);
    GPIO_write(1, GPIO_PIN_HIGH);
#elif defined (SOC_J721E)
    /* Enable the TCAN on GESI board.
     * Main Domain MCAN instances 4,5,6,7,9,11.
     */
    GPIO_write(0, GPIO_PIN_LOW);

    /* Enable MCU MCAN 1, WKUP_GPIO0_2. */
    GPIOSetDirMode_v0(CSL_WKUP_GPIO0_BASE, 2, GPIO_DIRECTION_OUTPUT);
    GPIOPinWrite_v0(CSL_WKUP_GPIO0_BASE, 2, GPIO_PIN_LOW);

    /* Enable MCU MCAN 0, WKUP_GPIO0_0, WKUP_GPIO0_54 */
    GPIOSetDirMode_v0(CSL_WKUP_GPIO0_BASE, 0, GPIO_DIRECTION_OUTPUT);
    GPIOPinWrite_v0(CSL_WKUP_GPIO0_BASE, 0, GPIO_PIN_HIGH);
    GPIOSetDirMode_v0(CSL_WKUP_GPIO0_BASE, 54, GPIO_DIRECTION_OUTPUT);
    GPIOPinWrite_v0(CSL_WKUP_GPIO0_BASE, 54, GPIO_PIN_HIGH);

    /* Enable Main MCAN 2, GPIO0_127. */
    GPIO_write(1, GPIO_PIN_LOW);

    /*
     * Configuring TCA6424 IO Exp 2 with addr 0x22
     * This io expander is controlled by i2c0
     * For Main MCAN2 P13 and P14 should be set to 0, This should route the MCAN2 STB line to transciver.
     * For Main MCAN0 P06 and P07 should be set to 1.
     */
    /* I2C initialization */
    I2C_init();
    I2C_Params_init(&i2cParams);
    i2cParams.transferMode = I2C_MODE_BLOCKING;
    i2cParams.bitRate = I2C_400kHz;
    i2cParams.transferCallbackFxn = NULL;

    handle = I2C_open(0U, &i2cParams);
    printf("I2C_open .........\n");

    dataToSlave[0] = TCA6424_REG_CONFIG0 | TCA6424_CMD_AUTO_INC;
    dataToSlave[1] = 0x0U;
    SetupI2CTransfer(handle, 0x23, &dataToSlave[0], 2, NULL, 0);
    printf("SetupI2CTransfer .........\n");

    dataToSlave[0] = TCA6424_REG_INPUT0 | TCA6424_CMD_AUTO_INC;
    dataToSlave[1] = 0x0U;
    dataToSlave[2] = 0x0U;
    dataToSlave[3] = 0x0U;
    SetupI2CTransfer(handle, 0x23, &dataToSlave[0], 1, &dataToSlave[1], 3);

    /* Set P06 and P07 to 1.
     * Set P13 and P14 to 0.
     */
    dataToSlave[0] = TCA6424_REG_OUTPUT0 | TCA6424_CMD_AUTO_INC;
    dataToSlave[1] |= 0xC0;
    dataToSlave[2] &= ~(0x18);
    SetupI2CTransfer(handle, 0x23, &dataToSlave[0], 1, &dataToSlave[1], 3);
#endif
}
#if defined(R5F) && defined(SYSBIOS)
int32_t appMcan2Init(void)
{
    int32_t                    configStatus = CSL_PASS;
    uint32_t                  /* mode         = 0U, */loopCnt = 0U;

    /* Do Pad Config for UART and MCAN */
    padConfig_prcmEnable();

    UART_printf("\n START MCAN2 INIT....\n");

    /* CrossBar Configuration */
    configStatus = App_mcanXBarConfig();

    /* Initialize message to transmit */
    txMsg.id  = (uint32_t)((uint32_t)(0x4U) << 18U);
    txMsg.rtr = 0U;
    txMsg.xtd = 0U;
    txMsg.esi = 0U;
    txMsg.dlc = 0xFU;
    txMsg.brs = 1U;
    txMsg.fdf = 0u;//1U;
    txMsg.efc = 1U;
    txMsg.mm  = 0xAAU;
    for (loopCnt = 0; loopCnt < MCAN_MAX_PAYLOAD_BYTES; loopCnt++)
    {
        txMsg.data[loopCnt] = 0;
    }
    configStatus = App_mcanConfig();
#if TX_CODE
    Tx_Timer_task();
#elif RX_CODE
    Rx_Timer_task();
#elif TX_RX_CODE
    Rx_Timer_task();
    Tx_Timer_task();
#else
#endif

    UART_printf("\n MCAN2 INIT END..........\n");

    return 0;
}
#endif

/* ========================================================================== */
/*                 Internal Function Definitions                              */
/* ========================================================================== */
static int32_t App_mcanRegisterInterrupt(uint32_t intNum, void f(uintptr_t))
{
    int32_t configStatus = STW_SOK;
    OsalRegisterIntrParams_t    intrPrms;
    OsalInterruptRetCode_e      osalRetVal;
    HwiP_Handle                 hwiHandle = NULL;

    /* Enable CPU Interrupts and register ISR - MCAN0 Intr0 */
    Osal_RegisterInterrupt_initParams(&intrPrms);
    /* Populate the interrupt parameters */
    intrPrms.corepacConfig.arg              = (uintptr_t) NULL;
    intrPrms.corepacConfig.isrRoutine       = f;
    intrPrms.corepacConfig.priority         = 0U;
    intrPrms.corepacConfig.corepacEventNum  = 0U;
    intrPrms.corepacConfig.intVecNum        = intNum;

    /* Register interrupts */
    osalRetVal = Osal_RegisterInterrupt(&intrPrms, &hwiHandle);
    if(OSAL_INT_SUCCESS != osalRetVal)
    {
        configStatus = CSL_EFAIL;
    }
    return configStatus;
}

static int32_t App_mcanXBarConfig(void)
{
    int32_t configStatus = STW_SOK;
    /* Main MCAN Inst 2 */
#if TX_CODE
    configStatus =  App_mcanRegisterInterrupt(APP_MAIN_MCAN_2_INT0, &App_mcanIntr0ISR);
#elif RX_CODE
    configStatus = App_mcanRegisterInterrupt (APP_MAIN_MCAN_2_INT1, &App_mcanIntr1ISR);
#else
    configStatus = App_mcanRegisterInterrupt (APP_MAIN_MCAN_2_INT0, &App_mcanIntr01ISR);
#endif
    if(STW_SOK != configStatus)
    {
        UART_printf("CrossBar/Interrupt Configuration failed.\n");
    }
    else
    {
        UART_printf("CrossBar/Interrupt Configuration done.\n");
    }

    return configStatus;
}

static int32_t App_mcanConfig(void)
{
    uint32_t                   fdoe;
    int32_t                    configStatus = CSL_PASS;
    MCAN_RevisionId            revId;
    MCAN_InitParams            initParams;
    MCAN_StdMsgIDFilterElement stdFiltelem;
    MCAN_BitTimingParams       bitTimes;

    /* Initialize MCAN Init params */
#ifdef MCAN_500KBPS
    initParams.fdMode          = 0x0U;
#else
    initParams.fdMode          = 0x1U;
#endif
    initParams.brsEnable       = 0x1U;
    initParams.txpEnable       = 0x0U;
    initParams.efbi            = 0x0U;
    initParams.pxhddisable     = 0x0U;
    initParams.darEnable       = 0x1U;
    initParams.wkupReqEnable   = 0x1U;
    initParams.autoWkupEnable  = 0x1U;
    initParams.emulationEnable = 0x1U;
    initParams.emulationFAck   = 0x0U;
    initParams.clkStopFAck     = 0x0U;
    initParams.wdcPreload      = 0xFFU;
    initParams.tdcEnable       = 0x1U;
    initParams.tdcConfig.tdcf  = 0xAU;
    initParams.tdcConfig.tdco  = 0x6U;
    /* Initialize MCAN Config params */
    configParams.monEnable         = 0x0U;
    configParams.asmEnable         = 0x0U;
    configParams.tsPrescalar       = 0xFU;
    configParams.tsSelect          = 0x0U;
    configParams.timeoutSelect     = MCAN_TIMEOUT_SELECT_CONT;
    configParams.timeoutPreload    = 0xFFFFU;
    configParams.timeoutCntEnable  = 0x0U;
    configParams.filterConfig.rrfs = 0x1U;
    configParams.filterConfig.rrfe = 0x1U;
    configParams.filterConfig.anfe = 0x1U;
    configParams.filterConfig.anfs = 0x1U;
    /* Initialize Message RAM Sections Configuration Parameters */
    msgRAMConfigParams.flssa                = APP_MCAN_STD_ID_FILT_START_ADDR;
    msgRAMConfigParams.lss                  = APP_MCAN_STD_ID_FILTER_NUM;
    msgRAMConfigParams.flesa                = APP_MCAN_EXT_ID_FILT_START_ADDR;
    msgRAMConfigParams.lse                  = APP_MCAN_EXT_ID_FILTER_NUM;
    msgRAMConfigParams.txStartAddr          = APP_MCAN_TX_BUFF_START_ADDR;
    msgRAMConfigParams.txBufNum             = APP_MCAN_TX_BUFF_SIZE;
    msgRAMConfigParams.txFIFOSize           = 0U;
    msgRAMConfigParams.txBufMode            = 0U;
    msgRAMConfigParams.txBufElemSize        = MCAN_ELEM_SIZE_64BYTES;
    msgRAMConfigParams.txEventFIFOStartAddr = APP_MCAN_TX_EVENT_START_ADDR;
    msgRAMConfigParams.txEventFIFOSize      = APP_MCAN_TX_BUFF_SIZE;
    msgRAMConfigParams.txEventFIFOWaterMark = 3U;
    msgRAMConfigParams.rxFIFO0startAddr     = APP_MCAN_FIFO_0_START_ADDR;
    msgRAMConfigParams.rxFIFO0size          = APP_MCAN_FIFO_0_NUM;
    msgRAMConfigParams.rxFIFO0waterMark     = 3U;
    msgRAMConfigParams.rxFIFO0OpMode        = 0U;
    msgRAMConfigParams.rxFIFO1startAddr     = APP_MCAN_FIFO_1_START_ADDR;
    msgRAMConfigParams.rxFIFO1size          = APP_MCAN_FIFO_1_NUM;
    msgRAMConfigParams.rxFIFO1waterMark     = 3U;
    msgRAMConfigParams.rxFIFO1OpMode        = 0U;
    msgRAMConfigParams.rxBufStartAddr       = APP_MCAN_RX_BUFF_START_ADDR;
    msgRAMConfigParams.rxBufElemSize        = MCAN_ELEM_SIZE_64BYTES;
    msgRAMConfigParams.rxFIFO0ElemSize      = MCAN_ELEM_SIZE_64BYTES;
    msgRAMConfigParams.rxFIFO1ElemSize      = MCAN_ELEM_SIZE_64BYTES;
    /* Initialize Tx Buffer Config params */
    stdFiltelem.sfid2 = 0x0U;
    stdFiltelem.sfid1 = 0x0U;;//0x4U;
    stdFiltelem.sfec  = 0x0U;;//0x7U;
    stdFiltelem.sft   = 0x0U;
    /* Initialize bit timings
     * Configuring 1Mbps and 5Mbps as nominal and data bit-rate respectively */
#ifdef MCAN_500KBPS
    bitTimes.nomRatePrescalar   = 0xFU;
#else
    bitTimes.nomRatePrescalar   = 0x7U;
#endif
    bitTimes.nomTimeSeg1        = 0x5U;
    bitTimes.nomTimeSeg2        = 0x2U;
    bitTimes.nomSynchJumpWidth  = 0x0U;
    bitTimes.dataRatePrescalar  = 0x1U;
    bitTimes.dataTimeSeg1       = 0x3U;
    bitTimes.dataTimeSeg2       = 0x2U;
    bitTimes.dataSynchJumpWidth = 0x0U;

    /* Get MCANSS Revision ID */
    MCAN_getRevisionId(gMcanModAddr, &revId);
    UART_printf("MCANSS Revision ID:\n");
    UART_printf("scheme:0x%x\n", revId.scheme);
    UART_printf("Business Unit:0x%x\n", revId.bu);
    UART_printf("Module ID:0x%x\n", revId.modId);
    UART_printf("RTL Revision:0x%x\n", revId.rtlRev);
    UART_printf("Major Revision:0x%x\n", revId.major);
    UART_printf("Custom Revision:0x%x\n", revId.custom);
    UART_printf("Minor Revision:0x%x\n", revId.minor);
    /* Enable Auto wakeup */
    fdoe = MCAN_isFDOpEnable(gMcanModAddr);
    if ((uint32_t)TRUE == fdoe)
    {
        UART_printf("CAN-FD operation is enabled through E-Fuse.\n");
    }
    else
    {
        UART_printf("CAN-FD operation is disabled through E-Fuse.\n");
    }
    /* wait for memory initialization to happen */
    while (FALSE == MCAN_isMemInitDone(gMcanModAddr))
    {}
    /* Get endianess value */
    UART_printf("Endianess Value: 0x%x\n",
                       MCAN_getEndianVal(gMcanModAddr));
    /* Put MCAN in SW initialization mode */
    MCAN_setOpMode(gMcanModAddr, MCAN_OPERATION_MODE_SW_INIT);
    while (MCAN_OPERATION_MODE_SW_INIT != MCAN_getOpMode(gMcanModAddr))
    {}
    /* Initialize MCAN module */
    MCAN_init(gMcanModAddr, &initParams);
    /* Configure MCAN module */
    MCAN_config(gMcanModAddr, &configParams);
    /* Configure Bit timings */
    MCAN_setBitTime(gMcanModAddr, &bitTimes);
    /* Set Extended ID Mask */
    MCAN_setExtIDAndMask(gMcanModAddr, APP_MCAN_EXT_ID_AND_MASK);
    /* Configure Message RAM Sections */
    MCAN_msgRAMConfig(gMcanModAddr, &msgRAMConfigParams);
    /* Configure Standard ID filter element */
    MCAN_addStdMsgIDFilter(gMcanModAddr, 0U, &stdFiltelem);
    /* Take MCAN out of the SW initialization mode */
    MCAN_setOpMode(gMcanModAddr, MCAN_OPERATION_MODE_NORMAL);
    while (MCAN_OPERATION_MODE_NORMAL != MCAN_getOpMode(gMcanModAddr))
    {}

    /* Enable Interrupts */
    MCAN_enableIntr(gMcanModAddr, MCAN_INTR_MASK_ALL, (uint32_t)TRUE);
    MCAN_enableIntr(gMcanModAddr,
                    MCAN_INTR_SRC_RES_ADDR_ACCESS, (uint32_t)FALSE);

    /* Select Interrupt Line */
    MCAN_selectIntrLine(APP_MCAN2_BASEADDR,
                        MCAN_INTR_MASK_ALL,
                        MCAN_INTR_LINE_NUM_0);

    /* Enable Interrupt Line */
    MCAN_enableIntrLine(APP_MCAN2_BASEADDR,
                        MCAN_INTR_LINE_NUM_0,
                        1U);
    return configStatus;
}

static void App_mcanIntr0ISR(uintptr_t arg)
{
    uint32_t intrStatus;

    intrStatus = MCAN_getIntrStatus(gMcanModAddr);
    MCAN_clearIntrStatus(gMcanModAddr, intrStatus);
#if TX_CODE
    if (MCAN_INTR_SRC_TRANS_COMPLETE ==
        (intrStatus & MCAN_INTR_SRC_TRANS_COMPLETE))
    {
        SemaphoreP_post(TxgSyncSem);
    }
#endif
}

static void App_mcanIntr1ISR(uintptr_t arg)
{
    //uint32_t intrStatus;

    gMcanIsrIntr1Status = MCAN_getIntrStatus(gMcanModAddr);
    MCAN_clearIntrStatus(gMcanModAddr, gMcanIsrIntr1Status);
#if RX_CODE
    if(((gMcanIsrIntr1Status & MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ==
                                    MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ||
        ((gMcanIsrIntr1Status & MCAN_INTR_SRC_RX_FIFO1_NEW_MSG) ==
                                    MCAN_INTR_SRC_RX_FIFO1_NEW_MSG))
//    if (MCAN_INTR_SRC_DEDICATED_RX_BUFF_MSG ==
//        (intrStatus & MCAN_INTR_SRC_DEDICATED_RX_BUFF_MSG))
    {
        SemaphoreP_post(RxgSyncSem);
    }
#endif
}

static void App_mcanIntr01ISR(uintptr_t arg)
{
#if 1//TX_RX_CODE
    gMcanIsrIntr1Status = MCAN_getIntrStatus(gMcanModAddr);
    MCAN_clearIntrStatus(gMcanModAddr, gMcanIsrIntr1Status);
    if (MCAN_INTR_SRC_TRANS_COMPLETE ==
        (gMcanIsrIntr1Status & MCAN_INTR_SRC_TRANS_COMPLETE))
    {
        SemaphoreP_post(TxgSyncSem);
    }

    if(((gMcanIsrIntr1Status & MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ==
         MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ||
       ((gMcanIsrIntr1Status & MCAN_INTR_SRC_RX_FIFO1_NEW_MSG) ==
         MCAN_INTR_SRC_RX_FIFO1_NEW_MSG))
    {
        SemaphoreP_post(RxgSyncSem);
    }
#endif
}

static void App_mcanTSIntrISR(uintptr_t arg)
{
    UART_printf("Time Stamp overflow happened.\n");
}

int32_t appRemoteServiceMcan2Init()
{
    int32_t status = 0;

    status = appRemoteServiceRegister(
        APP_REMOTE_SERVICE_MCAN2_NAME, appRemoteServiceMCAN2Handler);
    if(status!=0)
    {
        UART_printf(
            " REMOTE_SERVICE_MCAN2: ERROR: Unable to register remote service MCAN2 handler\n");
    }
    else
    {
        UART_printf(
                    " REMOTE_SERVICE_MCAN2: Able to register remote service MCAN2 handler\n");
    }
    return status;
}

int32_t appRemoteServiceMcan2DeInit()
{
    int32_t status = 0;

    status = appRemoteServiceUnRegister(APP_REMOTE_SERVICE_MCAN2_NAME);
    if(status!=0)
    {
        UART_printf(
            " REMOTE_SERVICE_MCAN2: ERROR: Unable to register remote service MCAN2 handler\n");
    }

    return status;
}

int32_t appRemoteServiceMCAN2Handler(char *service_name, uint32_t cmd,
    void *prm, uint32_t prm_size, uint32_t flags)
{
    int32_t  status = CSL_PASS;
    int i;
    if(prm!=NULL && prm_size == sizeof(uint32_t))
     {
         uintptr_t addr = (uintptr_t)(*(volatile uint32_t*)prm);
         //uint32_t value = *(volatile uint32_t*)addr;

         uint32_t *cmd_prms = (volatile uint32_t*)addr;
         appMemCacheInv((void*)addr, 256);
         for(i = 0;i< 10;i++)
         {
             printf("MCU2_1 : %d,\t",cmd_prms[i]);
         }
         printf("\n");
     }
#if 0
    MCAN_ProtocolStatus protStatus;

   st_OP_Signal_1 pd_dcan_msg_final;
   st_OP_Signal_0 pd_dcan_msg;
   st_Tracker pd_trk_msg;
   st_meta_data p_meta_data;

   /* Select Interrupt Line */
   MCAN_selectIntrLine(gMcanModAddr,
                       MCAN_INTR_MASK_ALL,
                       MCAN_INTR_LINE_NUM_0);

   uint32_t obj = 0,loopCnt = 0,obj_count = 0;
   if(cmdPrms->temp_data[0].status==STATUS_FILLED)
   {
       /* Enable Interrupt Line */
       MCAN_enableIntrLine(gMcanModAddr,
                           MCAN_INTR_LINE_NUM_0,
                           1U);
       /* Enable Transmission interrupt */
       status = MCAN_txBufTransIntrEnable(gMcanModAddr,
                                              1U,
                                              (uint32_t)TRUE);

       for (obj = 0; obj < (NUM_OF_OBJECTS * 2) + 1; obj++)
       {
           txMsg.id  = (uint32_t)((uint32_t)(mcan2TxMsgId[obj]) << 18U);

           for (loopCnt = 0; loopCnt < 8; loopCnt++)
           {
               pd_dcan_msg_final.pd_msg[loopCnt] = 0;
           }
           if(obj < 20)
           {
                //Copy all signals
                pd_dcan_msg.dist_x = (cmdPrms->temp_data[obj].long_distance);
                pd_dcan_msg.dist_y = (cmdPrms->temp_data[obj].lat_distance);
                pd_dcan_msg.vel_y = (cmdPrms->temp_data[obj].ped_Speed_y);
                pd_dcan_msg.vel_x = (cmdPrms->temp_data[obj].ped_Speed_x);


                pd_dcan_msg.obj_type = 5;//cmdPrms[obj].object_type;
                pd_dcan_msg.roll_count = rolling_count;

                //Convert all signals to be signed
                pd_dcan_msg_final.st_PD_Fields.obj_type = pd_dcan_msg.obj_type;
                pd_dcan_msg_final.st_PD_Fields.roll_count = pd_dcan_msg.roll_count;

                pd_dcan_msg_final.st_PD_Fields.dist_x = (pd_dcan_msg.dist_x + 8192);
                pd_dcan_msg_final.st_PD_Fields.vel_x = (pd_dcan_msg.vel_x + 4096);
                pd_dcan_msg_final.st_PD_Fields.dist_y = (pd_dcan_msg.dist_y + 8192);
                pd_dcan_msg_final.st_PD_Fields.vel_y = (pd_dcan_msg.vel_y + 4096);

                for (loopCnt = 0; loopCnt < 8; loopCnt++)
                {
                    txMsg.data[loopCnt] = pd_dcan_msg_final.pd_msg[loopCnt];
                }
           }
           else if(obj < 40)
           {
               pd_trk_msg.st_PD_Tracker.B_ID = (cmdPrms->temp_data[obj_count].tracking_id);
               pd_trk_msg.st_PD_Tracker.B_Status = (cmdPrms->temp_data[obj_count].tracking_status);
               pd_trk_msg.st_PD_Tracker.roll_count = rolling_count;
               pd_trk_msg.st_PD_Tracker.Ang_Left = 163.83;
               pd_trk_msg.st_PD_Tracker.Ang_Right = 163.83;
               pd_trk_msg.st_PD_Tracker.Range_Min_from_cam = 0;
               obj_count++;
               for (loopCnt = 0; loopCnt < 8; loopCnt++)
               {
                   txMsg.data[loopCnt] = pd_trk_msg.pd_msg[loopCnt];
               }
           }
           else
           {
               p_meta_data.st_meta_fields.overall_roll_count = rolling_count;
               p_meta_data.st_meta_fields.availability = 1;
               p_meta_data.st_meta_fields.num_objects = cmdPrms->num_of_objects;
               p_meta_data.st_meta_fields.stat_latency = cmdPrms->frame_latency;
               p_meta_data.st_meta_fields.stat_Dct = 1;
               p_meta_data.st_meta_fields.Debug_reserv_00 = 0;
               p_meta_data.st_meta_fields.Debug_reserv_01 = 0;
               p_meta_data.st_meta_fields.Debug_reserv_02 = 0;
               p_meta_data.st_meta_fields.Debug_reserv_03 = 0;
               p_meta_data.st_meta_fields.Debug_reserv_04 = 0;
               for (loopCnt = 0; loopCnt < 8; loopCnt++)
               {
                   txMsg.data[loopCnt] = p_meta_data.pd_msg[loopCnt];
               }
           }

           if (CSL_PASS != status)
           {
               UART_printf("\nError in enabling buffer Transmit interrupt...\n");
           }
           else
           {
               txMsg.dlc = 8;
               /* Write message to Msg RAM */
               MCAN_writeMsgRam(gMcanModAddr,
                                MCAN_MEM_TYPE_BUF,
                                1U,
                                &txMsg);
               /* Add request for transmission */
               status = MCAN_txBufAddReq(gMcanModAddr, 1U);
               if (CSL_PASS != status)
               {
                   UART_printf("\nError in Adding Transmission Request...\n");
                   break;
               }
               while (gMcanIsrIntr0Flag)
               {}
               gMcanIsrIntr0Flag = 1U;
               MCAN_getProtocolStatus(gMcanModAddr, &protStatus);

               /* Checking for Errors */
               if (((MCAN_ERR_CODE_NO_ERROR == protStatus.lastErrCode) ||
                    (MCAN_ERR_CODE_NO_CHANGE == protStatus.lastErrCode)) &&
                   ((MCAN_ERR_CODE_NO_ERROR == protStatus.dlec) ||
                    (MCAN_ERR_CODE_NO_CHANGE == protStatus.dlec)) &&
                   (0U == protStatus.pxe))
               {
//                       UART_printf(
//                           "\nMessage successfully transferred with payload Bytes:%d\n",
//                           gMcanAppdataSize[txMsg.dlc]);
               }
               else
               {
                   UART_printf(
                   "\nError in transmission with payload Bytes:%d\n",
                   gMcanAppdataSize[txMsg.dlc]);
                   status = CSL_EFAIL;
                   break;
               }
           }
       }

       //Rolling counter update
       if(rolling_count==63)
       {
           rolling_count=0;
       }
       else
       {
           rolling_count++;
       }
       cmdPrms->temp_data[0].status = STATUS_READY;
   }
#endif
   return status;
}



#if defined(R5F) && defined(SYSBIOS)
int32_t appMCAN2DeInit()
{
    /* MCAN2_deInit(); */

   return 0;
}
#endif

//Rx CODE STARTS//

void appMcanRxRun()
{

    int32_t              testStatus = CSL_PASS;
    MCAN_ErrCntStatus    errCounter;
    uint32_t timePeriodInMilliSec = 33; //3 sec
    MCAN_ProtocolStatus protStatus;
    uint32_t    readBuffNum, loopCnt;
    MCAN_RxFIFOStatus fifoStatus;
    while(1)
    {
        SemaphoreP_pend(RxgSyncSem, SemaphoreP_WAIT_FOREVER);
        {
            readBuffNum = 0U;
            loopCnt++;
            if(((gMcanIsrIntr1Status & MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ==
                                        MCAN_INTR_SRC_RX_FIFO0_NEW_MSG))
            {
                fifoStatus.num = (uint32_t)MCAN_RX_FIFO_NUM_0;
            }
            else
            {
                fifoStatus.num = (uint32_t)MCAN_RX_FIFO_NUM_1;
            }

            MCAN_getRxFIFOStatus(APP_MCAN2_BASEADDR, &fifoStatus);
            MCAN_readMsgRam(APP_MCAN2_BASEADDR,
                            MCAN_MEM_TYPE_FIFO,
                            fifoStatus.getIdx,
                            (uint32_t)fifoStatus.num,
                            &rxMsg);
            (void) MCAN_writeRxFIFOAck(APP_MCAN2_BASEADDR,
                                       (uint32_t)fifoStatus.num,
                                       fifoStatus.getIdx);

            MCAN_getProtocolStatus(APP_MCAN2_BASEADDR, &protStatus);

           /* Checking for Errors */
           if (((MCAN_ERR_CODE_NO_ERROR == protStatus.lastErrCode) ||
                (MCAN_ERR_CODE_NO_CHANGE == protStatus.lastErrCode)) &&
               ((MCAN_ERR_CODE_NO_ERROR == protStatus.dlec) ||
                (MCAN_ERR_CODE_NO_CHANGE == protStatus.dlec)) &&
               (0U == protStatus.pxe))
           {
               UART_printf("\n(%dth) Message successfully received.%d , %d, %d ,%d \n",
                           rxMsg.id,rxMsg.data[0],rxMsg.data[1],rxMsg.data[2],rxMsg.data[3]);
           }
           else
           {
               UART_printf("\nError in reception (%dth) message.\n",
                          loopCnt);
           }
        }


        if (CSL_EFAIL == testStatus)
        {
            UART_printf("\nRx Test FAILED...\n");
        }
        else
        {
            UART_printf("\nRx Test PASSED...\n");
        }
        /* Only limitation with this approach is that the Task_sleep()
         * can not provide a periodicity of less than 1 ms
         */
        Task_sleep(timePeriodInMilliSec);
     }

    /* Checking for Errors */
//        MCAN_getErrCounters(APP_MCAN2_BASEADDR, &errCounter);
//        if ((0U == errCounter.recErrCnt) &&
//            (0U == errCounter.canErrLogCnt))
//        {
//            MCAN_readMsgRam(APP_MCAN2_BASEADDR,
//                            MCAN_MEM_TYPE_BUF,
//                            0U,
//                            0U,
//                            &rxMsg);
//            UART_printf("data = %d %d %d %d \n",rxMsg.data[0],rxMsg.data[1],rxMsg.data[2],rxMsg.data[3]);
//        }
//        else
//        {
//            UART_printf(
//            "\nError in reception with payload Bytes:");
//            testStatus = CSL_EFAIL;
//        }
}

#ifdef TIMER_CALL
#if (TX_CODE) || (TX_RX_CODE)
static void Txtest()
{
   MCAN_ProtocolStatus protStatus;

   st_OP_Signal_1 pd_dcan_msg_final;
   st_OP_Signal_0 pd_dcan_msg;

   uint32_t obj = 0,loopCnt = 0,obj_count = 0;

   /* Enable Transmission interrupt */
   uint32_t status = MCAN_txBufTransIntrEnable(gMcanModAddr,
                                          1U,
                                          (uint32_t)TRUE);

   for (obj = 0; obj < (NUM_OF_OBJECTS); obj++)
   {
       txMsg.id  = (uint32_t)((uint32_t)(mcan2TxMsgId[obj]) << 18U);

       for (loopCnt = 0; loopCnt < 8; loopCnt++)
       {
           pd_dcan_msg_final.pd_msg[loopCnt] = 0;
       }
        //Copy all signals
        pd_dcan_msg.dist_x = 122;
        pd_dcan_msg.dist_y = 123;
        pd_dcan_msg.vel_y = 134;
        pd_dcan_msg.vel_x = 122;

        pd_dcan_msg.obj_type = 5;//cmdPrms[obj].object_type;

        //Convert all signals to be signed
        pd_dcan_msg_final.st_PD_Fields.obj_type = pd_dcan_msg.obj_type;
        pd_dcan_msg_final.st_PD_Fields.roll_count = pd_dcan_msg.roll_count;

        pd_dcan_msg_final.st_PD_Fields.dist_x = (pd_dcan_msg.dist_x + 8192);
        pd_dcan_msg_final.st_PD_Fields.vel_x = (pd_dcan_msg.vel_x + 4096);
        pd_dcan_msg_final.st_PD_Fields.dist_y = (pd_dcan_msg.dist_y + 8192);
        pd_dcan_msg_final.st_PD_Fields.vel_y = (pd_dcan_msg.vel_y + 4096);

        for (loopCnt = 0; loopCnt < 8; loopCnt++)
        {
            txMsg.data[loopCnt] = pd_dcan_msg_final.pd_msg[loopCnt];
        }


       if (CSL_PASS != status)
       {
           UART_printf("\nError in enabling buffer Transmit interrupt...\n");
       }
       else
       {
           txMsg.dlc = 8;
           /* Write message to Msg RAM */
           MCAN_writeMsgRam(gMcanModAddr,
                            MCAN_MEM_TYPE_BUF,
                            1U,
                            &txMsg);
           /* Add request for transmission */
           status = MCAN_txBufAddReq(gMcanModAddr, 1U);
           if (CSL_PASS != status)
           {
               UART_printf("\nError in Adding Transmission Request...\n");
               break;
           }
           //UART_printf("in semaphore pend\n");
           SemaphoreP_pend(TxgSyncSem, SemaphoreP_WAIT_FOREVER);
           //UART_printf("out semaphore pend\n");
           MCAN_getProtocolStatus(gMcanModAddr, &protStatus);

           /* Checking for Errors */
           if (((MCAN_ERR_CODE_NO_ERROR == protStatus.lastErrCode) ||
                (MCAN_ERR_CODE_NO_CHANGE == protStatus.lastErrCode)) &&
               ((MCAN_ERR_CODE_NO_ERROR == protStatus.dlec) ||
                (MCAN_ERR_CODE_NO_CHANGE == protStatus.dlec)) &&
               (0U == protStatus.pxe))
           {
            //UART_printf("\nMessage successfully transferred with payload Bytes \n");
           }
           else
           {
               UART_printf("\nError in transmission with payload Bytes:%d\n");
               status = CSL_EFAIL;
               break;
           }
       }
   }
}

#if defined(R5F) && defined(SYSBIOS)
void Tx_Timer_task()
{
    UART_printf("TASK SLEEP APPROACH \n");
    uint32_t timePeriodInMilliSec = 33;  //3 sec
    SemaphoreP_Params semParams;

    SemaphoreP_Params_init(&semParams);
    semParams.mode = SemaphoreP_Mode_COUNTING;
    TxgSyncSem = SemaphoreP_create(0U, &semParams);

    while(1)
    {
        //UART_printf("\n TX ................\n");
        Txtest();
        //UART_printf("\n RX ................\n");
        Rxtest();
        UART_printf("\n Task_sleep ................\n");

        Task_sleep(timePeriodInMilliSec);
    }
}
#endif
#endif

#if (RX_CODE) || (TX_RX_CODE)
#if defined(R5F) && defined(SYSBIOS)
static void Rxtest()
{
    int32_t              testStatus = CSL_PASS;
    MCAN_ErrCntStatus    errCounter;
    MCAN_ProtocolStatus protStatus;
    uint32_t    readBuffNum, loopCnt;
    MCAN_RxFIFOStatus fifoStatus;

    readBuffNum = 0U;
    loopCnt++;

    SemaphoreP_pend(RxgSyncSem, SemaphoreP_WAIT_FOREVER);

    if(((gMcanIsrIntr1Status & MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ==
                                MCAN_INTR_SRC_RX_FIFO0_NEW_MSG))
    {
        fifoStatus.num = (uint32_t)MCAN_RX_FIFO_NUM_0;
    }
    else
    {
        fifoStatus.num = (uint32_t)MCAN_RX_FIFO_NUM_1;
    }

    MCAN_getRxFIFOStatus(APP_MCAN2_BASEADDR, &fifoStatus);
    MCAN_readMsgRam(APP_MCAN2_BASEADDR,
                    MCAN_MEM_TYPE_FIFO,
                    fifoStatus.getIdx,
                    (uint32_t)fifoStatus.num,
                    &rxMsg);
    (void) MCAN_writeRxFIFOAck(APP_MCAN2_BASEADDR,
                               (uint32_t)fifoStatus.num,
                               fifoStatus.getIdx);

    MCAN_getProtocolStatus(APP_MCAN2_BASEADDR, &protStatus);

   /* Checking for Errors */
   if (((MCAN_ERR_CODE_NO_ERROR == protStatus.lastErrCode) ||
        (MCAN_ERR_CODE_NO_CHANGE == protStatus.lastErrCode)) &&
       ((MCAN_ERR_CODE_NO_ERROR == protStatus.dlec) ||
        (MCAN_ERR_CODE_NO_CHANGE == protStatus.dlec)) &&
       (0U == protStatus.pxe))
   {
//       UART_printf("\n(%dth) Message successfully received.%d , %d, %d ,%d \n",
//                   rxMsg.id,rxMsg.data[0],rxMsg.data[1],rxMsg.data[2],rxMsg.data[3]);
   }
   else
   {
       UART_printf("\nError in reception (%dth) message.\n",
                  loopCnt);
   }
}
void Rx_Timer_task()
{
    int32_t status = CSL_PASS;

    Board_pinmuxUpdate(gCockpitDemoPinmuxDataInfo,
                       BOARD_SOC_DOMAIN_MAIN);

    /* Set drive strength */
    CSL_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE +
            CSL_WKUP_CTRL_MMR_CFG0_H_IO_DRVSTRNGTH0_PROXY, 0xFU);

    CSL_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE +
            CSL_WKUP_CTRL_MMR_CFG0_V_IO_DRVSTRNGTH0_PROXY, 0xFU);

    SET_DEVICE_STATE(TISCI_DEV_MCAN2,
            TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
            status);

    SemaphoreP_Params semParams;

    SemaphoreP_Params_init(&semParams);
    semParams.mode = SemaphoreP_Mode_COUNTING;
    RxgSyncSem = SemaphoreP_create(0U, &semParams);
#if RX_CODE
    appMcanRxRun();
#endif
}
#endif

#endif
#endif

Thanks and Regards

Pooja

0 Karan Saxena over 4 years ago in reply to Pooja R1

TI__Guru* 75663 points

Hi Pooja,

There are a lot of #ifdefs in the code which are probably defined in some other header file. Can you please remove the piece of code that is not being used and send the source again? Or you can send the call sequence so that I can trace it in the existing .c file.

Can you also print the interrupt status in the else case in the ISR i.e. when there is no semaphore post? This would give us a data point showing what triggered the interrupt, it surely won't be a successful transmission as then the semaphore would be posted.

On how to trigger the Rx asynchronously, you need to have a separate task which always pends on the Rx semaphore being posted by the ISR, this way whenever the Rx event comes then the semaphore will be posted and the separate Rx task will get unblocked and then will execute.

Regards,

Karan

0 Pooja R1 over 4 years ago in reply to Karan Saxena

Intellectual 790 points

Hi Karan,

1. Code flow
- Entry to MCAN application using appMcan2Init() in appInit() [basic_demos/app_tirtos/common/app_init.c]
- Semaphore handle related to Rx created in Rx_Timer_task().
- Tx_Timer_task : Inside while(1), Txtest performs transmission and Rxtest performs reception.

7382.app_mcan2.c

/*
 *   Copyright (c) Texas Instruments Incorporated 2016-2019
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

/**
 *  \file     app_mcan2.c
 *
 *  \brief    This file contains MCAN sample code.
 *
 *  \details  MCAN operational mode is set to Classic CAN.
 *
 */

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
#define TIMER_CALL

#include <stdint.h>
#include <stdio.h>
#include <ti/csl/csl_types.h>
#include <ti/csl/soc.h>
#include <ti/csl/hw_types.h>
#include <ti/csl/arch/csl_arch.h>
#include <ti/csl/csl_mcan.h>
#include <ti/drv/uart/UART.h>
#include <ti/drv/uart/UART_stdio.h>
#include <ti/osal/osal.h>
#include <ti/drv/gpio/GPIO.h>
#include <ti/drv/gpio/soc/GPIO_soc.h>
#include <ti/csl/csl_gpio.h>
#include <ti/board/board.h>
#include <ti/drv/i2c/I2C.h>
#if defined (SOC_J721E)
#include <ti/drv/sciclient/sciclient.h>
#endif
#include <utils/mcan/app_mcan2.h>
#include <utils/remote_service/include/app_remote_service.h>
#include <utils/console_io/include/app_log.h>

#include <ti/drv/ipc/ipc.h>
#include <ti/osal/SemaphoreP.h>
#include "app_CAN_reader.h"
#include "app_sciclient_helper.h"
#include <ti/sysbios/knl/Task.h>

#include <ti/board/src/j721e_evm/include/board_cfg.h>
#include <ti/board/src/j721e_evm/include/board_pinmux.h>
#include <ti/csl/soc/cslr_soc_ctrl_mmr.h>
#ifdef TIMER_CALL
#include <ti/sysbios/timers/dmtimer/Timer.h>
#include <ti/osal/TimerP.h>
#include <ti/drv/uart/UART_stdio.h>
#include <ti/drv/uart/UART.h>

Timer_Handle timerHandle;

static uint32_t gMcanTask = 1U;
void (*fp_taskFxn)();
volatile uint32_t debugVar = 1U;
uint32_t numTimerTaskHit = 0;
#endif
/* ========================================================================== */
/*                                Macros                                      */
/* ========================================================================== */
#if defined (SOC_AM65XX)
#define APP_ENABLE_UART_PRINT                    (1U)
#elif defined (SOC_J721E)
#define APP_ENABLE_UART_PRINT                    (1U)
#endif

#define APP_MCAN_STD_ID_FILT_START_ADDR          (0U)
#define APP_MCAN_STD_ID_FILTER_NUM               (1U)
#define APP_MCAN_EXT_ID_FILT_START_ADDR          (48U)
#define APP_MCAN_EXT_ID_FILTER_NUM               (1U)
#define APP_MCAN_TX_EVENT_START_ADDR             (100U)
#define APP_MCAN_TX_EVENT_SIZE                   (5U)
#define APP_MCAN_TX_BUFF_START_ADDR              (148U)
#define APP_MCAN_TX_BUFF_SIZE                    (5U)
#define APP_MCAN_TX_FIFO_SIZE                    (5U)
#define APP_MCAN_FIFO_0_START_ADDR               (548U)
#define APP_MCAN_FIFO_0_NUM                      (5U)
#define APP_MCAN_FIFO_1_START_ADDR               (748U)
#define APP_MCAN_FIFO_1_NUM                      (5U)
#define APP_MCAN_RX_BUFF_START_ADDR              (948U)

#define APP_MCAN_EXT_ID_AND_MASK                 (0x1FFFFFFFU)

#define APP_MCU_MCAN_0_INT0                                   (0U)
#define APP_MCU_MCAN_0_INT1                                   (1U)
#define APP_MCU_MCAN_0_TS_INT                                 (4U)
#define APP_MCU_MCAN_1_INT0                                   (2U)
#define APP_MCU_MCAN_1_INT1                                   (3U)
#define APP_MCU_MCAN_1_TS_INT                                 (5U)

#define I2C_BUS_NUM                     (0)
#define TCA6424_SLAVE_ADDR              ((uint8_t) 0x23U)

#define TCA6424_CMD_AUTO_INC            ((uint8_t) 0x80U)

#if defined (SOC_J721E)
#if defined (BUILD_MCU1_0)
#define APP_MAIN_MCAN_2_INT0                (CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0)
#define APP_MAIN_MCAN_2_INT1                (CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_1)
#define APP_MAIN_MCAN_2_TS_INT              (CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_2)
#else
#define APP_MAIN_MCAN_0_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN0_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_0_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN0_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_0_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_2_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN2_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_2_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN2_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_2_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN2_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_4_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN4_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_4_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN4_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_4_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN4_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_5_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN5_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_5_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN5_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_5_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN5_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_6_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN6_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_6_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN6_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_6_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN6_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_7_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN7_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_7_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN7_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_7_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN7_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_9_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN9_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_9_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN9_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_9_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN9_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_11_INT0               (CSLR_R5FSS1_CORE0_INTR_MCAN11_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_11_INT1               (CSLR_R5FSS1_CORE0_INTR_MCAN11_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_11_TS_INT             (CSLR_R5FSS1_CORE0_INTR_MCAN11_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#endif
#endif

/* Print buffer character limit for prints- UART or CCS Console */
#define APP_PRINT_BUFFER_SIZE                       (4000)
#if defined (SOC_AM65XX)
/* Port and pin number mask for GPIO Load pin.
   Bits 7-0: Pin number  and Bits 15-8: Port number */
#define AM65XX_IDK_GPIO_CAN0_STB_PIN    (0x012F)
#define AM65XX_IDK_GPIO_CAN1_STB_PIN    (0x0143)
#endif
#if defined (SOC_J721E)
#define J721E_GPIO_GESI_CAN_STB_PIN     (0x003C)
#define J721E_GPIO_MAIN_MCAN2_STB_PIN   (0x007F)
#endif
/*****************************/
/*****************************/
#define TX_CODE 0
#define RX_CODE 0
#define TX_RX_CODE 1

volatile uint32_t gMcanIsrIntr1Status;
/*****************************/
/*****************************/
/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */
#define APP_USE_CAN
#if defined (APP_USE_CAN)
static pinmuxPerCfg_t gMcan2PinCfg[] =
{
    /* MyMCAN2 -> MCAN2_RX -> AC2 */
    {
        PIN_UART0_CTSN, PIN_MODE(3) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCAN2 -> MCAN2_TX -> AB1 */
    {
        PIN_UART0_RTSN, PIN_MODE(3) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gI2c0PinCfg[] =
{
    /* MyI2C0 -> I2C0_SCL -> AC5 */
    {
        PIN_I2C0_SCL, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    /* MyI2C0 -> I2C0_SDA -> AA5 */
    {
        PIN_I2C0_SDA, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gGpio0PinCfg[] =
{
    /* MyGPIO0 -> GPIO0_127 -> AC4 */
    {
        PIN_UART1_CTSN, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gMcanPinCfg[] =
{
    {0, TRUE, gMcan2PinCfg},
    {1, TRUE, gI2c0PinCfg},
    {2, TRUE, gGpio0PinCfg},
    {PINMUX_END}
};
#endif

static pinmuxBoardCfg_t gCockpitDemoPinmuxDataInfo[] =
{
#if defined (APP_USE_CAN)
    {1, gMcanPinCfg},
#endif
    {PINMUX_END}
};

uint32_t          gMcanAppdataSize[16] =
{0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
volatile uint32_t gMcanIsrIntr0Flag = 1U;
//volatile uint32_t gMcanIsrIntr1Flag = 1U;
SemaphoreP_Handle RxgSyncSem;
SemaphoreP_Handle TxgSyncSem;
MCAN_ECCErrStatus gMcaneccErr;
#define APP_MCAN2_BASEADDR                       (CSL_MCAN2_MSGMEM_RAM_BASE)
uint32_t gMcanModAddr = APP_MCAN2_BASEADDR;

MCAN_TxBufElement          txMsg;
MCAN_RxBufElement    rxMsg;
MCAN_MsgRAMConfigParams    msgRAMConfigParams;
MCAN_ConfigParams          configParams;

const uint32_t mcan2TxMsgId[] = {OBJ_MSG_ID1,OBJ_MSG_ID2,OBJ_MSG_ID3,OBJ_MSG_ID4,OBJ_MSG_ID5,OBJ_MSG_ID6,OBJ_MSG_ID7,OBJ_MSG_ID8,OBJ_MSG_ID9,OBJ_MSG_ID10,OBJ_MSG_ID11,OBJ_MSG_ID12,OBJ_MSG_ID13,OBJ_MSG_ID14,OBJ_MSG_ID15,OBJ_MSG_ID16,OBJ_MSG_ID17,OBJ_MSG_ID18,OBJ_MSG_ID19,OBJ_MSG_ID20,\
                                 OBJ_MSG_ID21,OBJ_MSG_ID22,OBJ_MSG_ID23,OBJ_MSG_ID24,OBJ_MSG_ID25,OBJ_MSG_ID26,OBJ_MSG_ID27,OBJ_MSG_ID28,OBJ_MSG_ID29,OBJ_MSG_ID30,OBJ_MSG_ID31,OBJ_MSG_ID32,OBJ_MSG_ID33,OBJ_MSG_ID34,OBJ_MSG_ID35,OBJ_MSG_ID36,OBJ_MSG_ID37,OBJ_MSG_ID38,OBJ_MSG_ID39,\
                                 OBJ_MSG_ID40,OBJ_MSG_ID41
};



#if defined (SOC_J721E)
/* GPIO Driver board specific pin configuration structure */
GPIO_PinConfig gpioPinConfigs[] = {
    /* Output pin : CAN STB */
    J721E_GPIO_GESI_CAN_STB_PIN   | GPIO_CFG_OUTPUT,
    J721E_GPIO_MAIN_MCAN2_STB_PIN | GPIO_CFG_OUTPUT,
};
#endif

/* GPIO Driver call back functions */
GPIO_CallbackFxn gpioCallbackFunctions[] = {
    NULL
};

/* GPIO Driver configuration structure */
GPIO_v0_Config GPIO_v0_config = {
        gpioPinConfigs,
        gpioCallbackFunctions,
        sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
        sizeof(gpioCallbackFunctions) / sizeof(GPIO_CallbackFxn),
        0,
    };
/* ========================================================================== */
/*                 Internal Function Declarations                             */
/* ========================================================================== */

/**
 * \brief   This function will configure MCAN module
 *
 * \param   none.
 *
 * \retval  status      configuration status.
 */
static int32_t App_mcanConfig(void);
static void Rxtest();

int32_t appRemoteServiceMCAN2Handler(char *service_name, uint32_t cmd,
    void *prm, uint32_t prm_size, uint32_t flags);
/**
 * \brief   This function will configure X-BAR for MCAN interrupts
 *
 * \param   none.
 *
 * \retval  status      configuration status.
 */
static int32_t App_mcanXBarConfig(void);

/**
 * \brief   This is Interrupt Service Routine for MCAN interrupt 0.
 *
 * \param   none.
 *
 * \retval  none.
 */
static void App_mcanIntr0ISR(uintptr_t arg);
static void App_mcanIntr01ISR(uintptr_t arg);

/**
 * \brief   This is Interrupt Service Routine for MCAN interrupt 1.
 *
 * \param   none.
 *
 * \retval  none.
 */
static void App_mcanIntr1ISR(uintptr_t arg);

/**
 * \brief   This is Interrupt Service Routine for MCAN TimeStamp interrupt.
 *
 * \param   none.
 *
 * \retval  none.
 */
static void App_mcanTSIntrISR(uintptr_t arg);
/**
 * \brief   This API will load the register from ECC memory bank.
 *
 * \param   txMsg           message object to be transmitted.
 *
 * \return  None.
 */
static int32_t App_mcanRegisterInterrupt(uint32_t intNum, void f(uintptr_t));

/* ========================================================================== */
/*                          Function Definitions                              */
/* ========================================================================== */
#define TCA6424_CMD_AUTO_INC            ((uint8_t) 0x80U)

/* Input status register */
#define TCA6424_REG_INPUT0              ((UInt8) 0x00U)
#define TCA6424_REG_INPUT1              ((UInt8) 0x01U)
#define TCA6424_REG_INPUT2              ((UInt8) 0x02U)

/* Output register to change state of output BIT set to 1, output set HIGH */
#define TCA6424_REG_OUTPUT0             ((uint8_t) 0x04U)
#define TCA6424_REG_OUTPUT1             ((uint8_t) 0x05U)
#define TCA6424_REG_OUTPUT2             ((uint8_t) 0x06U)

/* Configuration register. BIT = '1' sets port to input, BIT = '0' sets
 * port to output */
#define TCA6424_REG_CONFIG0             ((uint8_t) 0x0CU)
#define TCA6424_REG_CONFIG1             ((uint8_t) 0x0DU)
#define TCA6424_REG_CONFIG2             ((uint8_t) 0x0EU)



void SetupI2CTransfer(I2C_Handle handle,  uint32_t slaveAddr,
                      uint8_t *writeData, uint32_t numWriteBytes,
                      uint8_t *readData,  uint32_t numReadBytes)
{
    bool status;
    I2C_Transaction i2cTransaction;

    I2C_transactionInit(&i2cTransaction);
    i2cTransaction.slaveAddress = slaveAddr;
    i2cTransaction.writeBuf = (uint8_t *)&writeData[0];
    i2cTransaction.writeCount = numWriteBytes;
    i2cTransaction.readBuf = (uint8_t *)&readData[0];
    i2cTransaction.readCount = numReadBytes;
    status = I2C_transfer(handle, &i2cTransaction);
    if(FALSE == status)
    {
        UART_printf("\n Data Transfer failed. \n");
    }
}

void padConfig_prcmEnable()
{
    /* UART Init */
    Board_initCfg   boardCfg;
    Board_STATUS    boardStatus;

#if defined (SOC_J721E)
    I2C_Params      i2cParams;
    I2C_Handle      handle = NULL;
    uint8_t         dataToSlave[4];
#endif

    boardCfg = BOARD_INIT_MODULE_CLOCK |
               BOARD_INIT_PINMUX_CONFIG;
#if (APP_ENABLE_UART_PRINT == 1)
    boardCfg |= BOARD_INIT_UART_STDIO;
#endif
    boardStatus = Board_init(boardCfg);
    if (boardStatus != BOARD_SOK)
    {
        UART_printf("[Error] Board init failed!!\n");
    }

    /* Pin mux for CAN STB used in GESI board */
    *(volatile unsigned int *)(0x0011c0f4) = 0x20007;
    /* Pinmux for MAIN_MCAN4 */
    *(volatile unsigned int *)(0x0011c020) = 0x60006;
    *(volatile unsigned int *)(0x0011c024) = 0x60006;
    /* Pinmux for MAIN_MCAN5 */
    *(volatile unsigned int *)(0x0011c04c) = 0x60006;
    *(volatile unsigned int *)(0x0011c050) = 0x60006;
    /* Pinmux for MAIN_MCAN6 */
    *(volatile unsigned int *)(0x0011c054) = 0x60006;
    *(volatile unsigned int *)(0x0011c06C) = 0x60006;
    /* Pinmux for MAIN_MCAN7 */
    *(volatile unsigned int *)(0x0011c074) = 0x60006;
    *(volatile unsigned int *)(0x0011c078) = 0x60006;
    /* Pinmux for MAIN_MCAN9 */
    *(volatile unsigned int *)(0x0011c0cc) = 0x60006;
    *(volatile unsigned int *)(0x0011c0d0) = 0x60006;
    /* Pinmux for MAIN_MCAN11 */
    *(volatile unsigned int *)(0x0011c11c) = 0x60006;
    *(volatile unsigned int *)(0x0011c120) = 0x60006;

    /* GPIO initialization */
    GPIO_init();

    /* Enable CAN transceivers by setting the STB pins */
#if defined (SOC_AM65XX)
    GPIO_write(0, GPIO_PIN_HIGH);
    GPIO_write(1, GPIO_PIN_HIGH);
#elif defined (SOC_J721E)
    /* Enable the TCAN on GESI board.
     * Main Domain MCAN instances 4,5,6,7,9,11.
     */
    GPIO_write(0, GPIO_PIN_LOW);

    /* Enable MCU MCAN 1, WKUP_GPIO0_2. */
    GPIOSetDirMode_v0(CSL_WKUP_GPIO0_BASE, 2, GPIO_DIRECTION_OUTPUT);
    GPIOPinWrite_v0(CSL_WKUP_GPIO0_BASE, 2, GPIO_PIN_LOW);

    /* Enable MCU MCAN 0, WKUP_GPIO0_0, WKUP_GPIO0_54 */
    GPIOSetDirMode_v0(CSL_WKUP_GPIO0_BASE, 0, GPIO_DIRECTION_OUTPUT);
    GPIOPinWrite_v0(CSL_WKUP_GPIO0_BASE, 0, GPIO_PIN_HIGH);
    GPIOSetDirMode_v0(CSL_WKUP_GPIO0_BASE, 54, GPIO_DIRECTION_OUTPUT);
    GPIOPinWrite_v0(CSL_WKUP_GPIO0_BASE, 54, GPIO_PIN_HIGH);

    /* Enable Main MCAN 2, GPIO0_127. */
    GPIO_write(1, GPIO_PIN_LOW);

    /*
     * Configuring TCA6424 IO Exp 2 with addr 0x22
     * This io expander is controlled by i2c0
     * For Main MCAN2 P13 and P14 should be set to 0, This should route the MCAN2 STB line to transciver.
     * For Main MCAN0 P06 and P07 should be set to 1.
     */
    /* I2C initialization */
    I2C_init();
    I2C_Params_init(&i2cParams);
    i2cParams.transferMode = I2C_MODE_BLOCKING;
    i2cParams.bitRate = I2C_400kHz;
    i2cParams.transferCallbackFxn = NULL;

    handle = I2C_open(0U, &i2cParams);
    printf("I2C_open .........\n");

    dataToSlave[0] = TCA6424_REG_CONFIG0 | TCA6424_CMD_AUTO_INC;
    dataToSlave[1] = 0x0U;
    SetupI2CTransfer(handle, 0x23, &dataToSlave[0], 2, NULL, 0);
    printf("SetupI2CTransfer .........\n");

    dataToSlave[0] = TCA6424_REG_INPUT0 | TCA6424_CMD_AUTO_INC;
    dataToSlave[1] = 0x0U;
    dataToSlave[2] = 0x0U;
    dataToSlave[3] = 0x0U;
    SetupI2CTransfer(handle, 0x23, &dataToSlave[0], 1, &dataToSlave[1], 3);

    /* Set P06 and P07 to 1.
     * Set P13 and P14 to 0.
     */
    dataToSlave[0] = TCA6424_REG_OUTPUT0 | TCA6424_CMD_AUTO_INC;
    dataToSlave[1] |= 0xC0;
    dataToSlave[2] &= ~(0x18);
    SetupI2CTransfer(handle, 0x23, &dataToSlave[0], 1, &dataToSlave[1], 3);
#endif
}
#if defined(R5F) && defined(SYSBIOS)
int32_t appMcan2Init(void)
{
    int32_t                    configStatus = CSL_PASS;
    uint32_t                  /* mode         = 0U, */loopCnt = 0U;

    /* Do Pad Config for UART and MCAN */
    padConfig_prcmEnable();

    UART_printf("\n START MCAN2 INIT....\n");

    /* CrossBar Configuration */
    configStatus = App_mcanXBarConfig();

    /* Initialize message to transmit */
    txMsg.id  = (uint32_t)((uint32_t)(0x4U) << 18U);
    txMsg.rtr = 0U;
    txMsg.xtd = 0U;
    txMsg.esi = 0U;
    txMsg.dlc = 0xFU;
    txMsg.brs = 1U;
    txMsg.fdf = 0u;//1U;
    txMsg.efc = 1U;
    txMsg.mm  = 0xAAU;
    for (loopCnt = 0; loopCnt < MCAN_MAX_PAYLOAD_BYTES; loopCnt++)
    {
        txMsg.data[loopCnt] = 0;
    }
    configStatus = App_mcanConfig();

    Rx_Timer_task();
    Tx_Timer_task();


    UART_printf("\n MCAN2 INIT END..........\n");

    return 0;
}
#endif

/* ========================================================================== */
/*                 Internal Function Definitions                              */
/* ========================================================================== */
static int32_t App_mcanRegisterInterrupt(uint32_t intNum, void f(uintptr_t))
{
    int32_t configStatus = STW_SOK;
    OsalRegisterIntrParams_t    intrPrms;
    OsalInterruptRetCode_e      osalRetVal;
    HwiP_Handle                 hwiHandle = NULL;

    /* Enable CPU Interrupts and register ISR - MCAN0 Intr0 */
    Osal_RegisterInterrupt_initParams(&intrPrms);
    /* Populate the interrupt parameters */
    intrPrms.corepacConfig.arg              = (uintptr_t) NULL;
    intrPrms.corepacConfig.isrRoutine       = f;
    intrPrms.corepacConfig.priority         = 0U;
    intrPrms.corepacConfig.corepacEventNum  = 0U;
    intrPrms.corepacConfig.intVecNum        = intNum;

    /* Register interrupts */
    osalRetVal = Osal_RegisterInterrupt(&intrPrms, &hwiHandle);
    if(OSAL_INT_SUCCESS != osalRetVal)
    {
        configStatus = CSL_EFAIL;
    }
    return configStatus;
}

static int32_t App_mcanXBarConfig(void)
{
    int32_t configStatus = STW_SOK;
    /* Main MCAN Inst 2 */
    configStatus = App_mcanRegisterInterrupt (APP_MAIN_MCAN_2_INT0, &App_mcanIntr01ISR);

    if(STW_SOK != configStatus)
    {
        UART_printf("CrossBar/Interrupt Configuration failed.\n");
    }
    else
    {
        UART_printf("CrossBar/Interrupt Configuration done.\n");
    }

    return configStatus;
}

static int32_t App_mcanConfig(void)
{
    uint32_t                   fdoe;
    int32_t                    configStatus = CSL_PASS;
    MCAN_RevisionId            revId;
    MCAN_InitParams            initParams;
    MCAN_StdMsgIDFilterElement stdFiltelem;
    MCAN_BitTimingParams       bitTimes;

    /* Initialize MCAN Init params */
#ifdef MCAN_500KBPS
    initParams.fdMode          = 0x0U;
#else
    initParams.fdMode          = 0x1U;
#endif
    initParams.brsEnable       = 0x1U;
    initParams.txpEnable       = 0x0U;
    initParams.efbi            = 0x0U;
    initParams.pxhddisable     = 0x0U;
    initParams.darEnable       = 0x1U;
    initParams.wkupReqEnable   = 0x1U;
    initParams.autoWkupEnable  = 0x1U;
    initParams.emulationEnable = 0x1U;
    initParams.emulationFAck   = 0x0U;
    initParams.clkStopFAck     = 0x0U;
    initParams.wdcPreload      = 0xFFU;
    initParams.tdcEnable       = 0x1U;
    initParams.tdcConfig.tdcf  = 0xAU;
    initParams.tdcConfig.tdco  = 0x6U;
    /* Initialize MCAN Config params */
    configParams.monEnable         = 0x0U;
    configParams.asmEnable         = 0x0U;
    configParams.tsPrescalar       = 0xFU;
    configParams.tsSelect          = 0x0U;
    configParams.timeoutSelect     = MCAN_TIMEOUT_SELECT_CONT;
    configParams.timeoutPreload    = 0xFFFFU;
    configParams.timeoutCntEnable  = 0x0U;
    configParams.filterConfig.rrfs = 0x1U;
    configParams.filterConfig.rrfe = 0x1U;
    configParams.filterConfig.anfe = 0x1U;
    configParams.filterConfig.anfs = 0x1U;
    /* Initialize Message RAM Sections Configuration Parameters */
    msgRAMConfigParams.flssa                = APP_MCAN_STD_ID_FILT_START_ADDR;
    msgRAMConfigParams.lss                  = APP_MCAN_STD_ID_FILTER_NUM;
    msgRAMConfigParams.flesa                = APP_MCAN_EXT_ID_FILT_START_ADDR;
    msgRAMConfigParams.lse                  = APP_MCAN_EXT_ID_FILTER_NUM;
    msgRAMConfigParams.txStartAddr          = APP_MCAN_TX_BUFF_START_ADDR;
    msgRAMConfigParams.txBufNum             = APP_MCAN_TX_BUFF_SIZE;
    msgRAMConfigParams.txFIFOSize           = 0U;
    msgRAMConfigParams.txBufMode            = 0U;
    msgRAMConfigParams.txBufElemSize        = MCAN_ELEM_SIZE_64BYTES;
    msgRAMConfigParams.txEventFIFOStartAddr = APP_MCAN_TX_EVENT_START_ADDR;
    msgRAMConfigParams.txEventFIFOSize      = APP_MCAN_TX_BUFF_SIZE;
    msgRAMConfigParams.txEventFIFOWaterMark = 3U;
    msgRAMConfigParams.rxFIFO0startAddr     = APP_MCAN_FIFO_0_START_ADDR;
    msgRAMConfigParams.rxFIFO0size          = APP_MCAN_FIFO_0_NUM;
    msgRAMConfigParams.rxFIFO0waterMark     = 3U;
    msgRAMConfigParams.rxFIFO0OpMode        = 0U;
    msgRAMConfigParams.rxFIFO1startAddr     = APP_MCAN_FIFO_1_START_ADDR;
    msgRAMConfigParams.rxFIFO1size          = APP_MCAN_FIFO_1_NUM;
    msgRAMConfigParams.rxFIFO1waterMark     = 3U;
    msgRAMConfigParams.rxFIFO1OpMode        = 0U;
    msgRAMConfigParams.rxBufStartAddr       = APP_MCAN_RX_BUFF_START_ADDR;
    msgRAMConfigParams.rxBufElemSize        = MCAN_ELEM_SIZE_64BYTES;
    msgRAMConfigParams.rxFIFO0ElemSize      = MCAN_ELEM_SIZE_64BYTES;
    msgRAMConfigParams.rxFIFO1ElemSize      = MCAN_ELEM_SIZE_64BYTES;
    /* Initialize Tx Buffer Config params */
    stdFiltelem.sfid2 = 0x0U;
    stdFiltelem.sfid1 = 0x0U;;//0x4U;
    stdFiltelem.sfec  = 0x0U;;//0x7U;
    stdFiltelem.sft   = 0x0U;
    /* Initialize bit timings
     * Configuring 1Mbps and 5Mbps as nominal and data bit-rate respectively */
#ifdef MCAN_500KBPS
    bitTimes.nomRatePrescalar   = 0xFU;
#else
    bitTimes.nomRatePrescalar   = 0x7U;
#endif
    bitTimes.nomTimeSeg1        = 0x5U;
    bitTimes.nomTimeSeg2        = 0x2U;
    bitTimes.nomSynchJumpWidth  = 0x0U;
    bitTimes.dataRatePrescalar  = 0x1U;
    bitTimes.dataTimeSeg1       = 0x3U;
    bitTimes.dataTimeSeg2       = 0x2U;
    bitTimes.dataSynchJumpWidth = 0x0U;

    /* Get MCANSS Revision ID */
    MCAN_getRevisionId(gMcanModAddr, &revId);
    UART_printf("MCANSS Revision ID:\n");
    UART_printf("scheme:0x%x\n", revId.scheme);
    UART_printf("Business Unit:0x%x\n", revId.bu);
    UART_printf("Module ID:0x%x\n", revId.modId);
    UART_printf("RTL Revision:0x%x\n", revId.rtlRev);
    UART_printf("Major Revision:0x%x\n", revId.major);
    UART_printf("Custom Revision:0x%x\n", revId.custom);
    UART_printf("Minor Revision:0x%x\n", revId.minor);
    /* Enable Auto wakeup */
    fdoe = MCAN_isFDOpEnable(gMcanModAddr);
    if ((uint32_t)TRUE == fdoe)
    {
        UART_printf("CAN-FD operation is enabled through E-Fuse.\n");
    }
    else
    {
        UART_printf("CAN-FD operation is disabled through E-Fuse.\n");
    }
    /* wait for memory initialization to happen */
    while (FALSE == MCAN_isMemInitDone(gMcanModAddr))
    {}
    /* Get endianess value */
    UART_printf("Endianess Value: 0x%x\n",
                       MCAN_getEndianVal(gMcanModAddr));
    /* Put MCAN in SW initialization mode */
    MCAN_setOpMode(gMcanModAddr, MCAN_OPERATION_MODE_SW_INIT);
    while (MCAN_OPERATION_MODE_SW_INIT != MCAN_getOpMode(gMcanModAddr))
    {}
    /* Initialize MCAN module */
    MCAN_init(gMcanModAddr, &initParams);
    /* Configure MCAN module */
    MCAN_config(gMcanModAddr, &configParams);
    /* Configure Bit timings */
    MCAN_setBitTime(gMcanModAddr, &bitTimes);
    /* Set Extended ID Mask */
    MCAN_setExtIDAndMask(gMcanModAddr, APP_MCAN_EXT_ID_AND_MASK);
    /* Configure Message RAM Sections */
    MCAN_msgRAMConfig(gMcanModAddr, &msgRAMConfigParams);
    /* Configure Standard ID filter element */
    MCAN_addStdMsgIDFilter(gMcanModAddr, 0U, &stdFiltelem);
    /* Take MCAN out of the SW initialization mode */
    MCAN_setOpMode(gMcanModAddr, MCAN_OPERATION_MODE_NORMAL);
    while (MCAN_OPERATION_MODE_NORMAL != MCAN_getOpMode(gMcanModAddr))
    {}

    /* Enable Interrupts */
    MCAN_enableIntr(gMcanModAddr, MCAN_INTR_MASK_ALL, (uint32_t)TRUE);
    MCAN_enableIntr(gMcanModAddr,
                    MCAN_INTR_SRC_RES_ADDR_ACCESS, (uint32_t)FALSE);

    /* Select Interrupt Line */
    MCAN_selectIntrLine(APP_MCAN2_BASEADDR,
                        MCAN_INTR_MASK_ALL,
                        MCAN_INTR_LINE_NUM_0);

    /* Enable Interrupt Line */
    MCAN_enableIntrLine(APP_MCAN2_BASEADDR,
                        MCAN_INTR_LINE_NUM_0,
                        1U);
    return configStatus;
}

static void App_mcanIntr01ISR(uintptr_t arg)
{
    gMcanIsrIntr1Status = MCAN_getIntrStatus(gMcanModAddr);
    MCAN_clearIntrStatus(gMcanModAddr, gMcanIsrIntr1Status);
    if (MCAN_INTR_SRC_TRANS_COMPLETE ==
        (gMcanIsrIntr1Status & MCAN_INTR_SRC_TRANS_COMPLETE))
    {
        SemaphoreP_post(TxgSyncSem);
    }

    if(((gMcanIsrIntr1Status & MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ==
         MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ||
       ((gMcanIsrIntr1Status & MCAN_INTR_SRC_RX_FIFO1_NEW_MSG) ==
         MCAN_INTR_SRC_RX_FIFO1_NEW_MSG))
    {
        SemaphoreP_post(RxgSyncSem);
    }
}

static void Txtest()
{
   MCAN_ProtocolStatus protStatus;

   st_OP_Signal_1 pd_dcan_msg_final;
   st_OP_Signal_0 pd_dcan_msg;

   uint32_t obj = 0,loopCnt = 0,obj_count = 0;

   /* Enable Transmission interrupt */
   uint32_t status = MCAN_txBufTransIntrEnable(gMcanModAddr,
                                          1U,
                                          (uint32_t)TRUE);

   for (obj = 0; obj < (NUM_OF_OBJECTS); obj++)
   {
       txMsg.id  = (uint32_t)((uint32_t)(mcan2TxMsgId[obj]) << 18U);

       for (loopCnt = 0; loopCnt < 8; loopCnt++)
       {
           pd_dcan_msg_final.pd_msg[loopCnt] = 0;
       }
        //Copy all signals
        pd_dcan_msg.dist_x = 122;
        pd_dcan_msg.dist_y = 123;
        pd_dcan_msg.vel_y = 134;
        pd_dcan_msg.vel_x = 122;

        pd_dcan_msg.obj_type = 5;//cmdPrms[obj].object_type;

        //Convert all signals to be signed
        pd_dcan_msg_final.st_PD_Fields.obj_type = pd_dcan_msg.obj_type;
        pd_dcan_msg_final.st_PD_Fields.roll_count = pd_dcan_msg.roll_count;

        pd_dcan_msg_final.st_PD_Fields.dist_x = (pd_dcan_msg.dist_x + 8192);
        pd_dcan_msg_final.st_PD_Fields.vel_x = (pd_dcan_msg.vel_x + 4096);
        pd_dcan_msg_final.st_PD_Fields.dist_y = (pd_dcan_msg.dist_y + 8192);
        pd_dcan_msg_final.st_PD_Fields.vel_y = (pd_dcan_msg.vel_y + 4096);

        for (loopCnt = 0; loopCnt < 8; loopCnt++)
        {
            txMsg.data[loopCnt] = pd_dcan_msg_final.pd_msg[loopCnt];
        }


       if (CSL_PASS != status)
       {
           UART_printf("\nError in enabling buffer Transmit interrupt...\n");
       }
       else
       {
           txMsg.dlc = 8;
           /* Write message to Msg RAM */
           MCAN_writeMsgRam(gMcanModAddr,
                            MCAN_MEM_TYPE_BUF,
                            1U,
                            &txMsg);
           /* Add request for transmission */
           status = MCAN_txBufAddReq(gMcanModAddr, 1U);
           if (CSL_PASS != status)
           {
               UART_printf("\nError in Adding Transmission Request...\n");
               break;
           }
           //UART_printf("in semaphore pend\n");
           SemaphoreP_pend(TxgSyncSem, SemaphoreP_WAIT_FOREVER);
           //UART_printf("out semaphore pend\n");
           MCAN_getProtocolStatus(gMcanModAddr, &protStatus);

           /* Checking for Errors */
           if (((MCAN_ERR_CODE_NO_ERROR == protStatus.lastErrCode) ||
                (MCAN_ERR_CODE_NO_CHANGE == protStatus.lastErrCode)) &&
               ((MCAN_ERR_CODE_NO_ERROR == protStatus.dlec) ||
                (MCAN_ERR_CODE_NO_CHANGE == protStatus.dlec)) &&
               (0U == protStatus.pxe))
           {
            //UART_printf("\nMessage successfully transferred with payload Bytes \n");
           }
           else
           {
               UART_printf("\nError in transmission with payload Bytes:%d\n");
               status = CSL_EFAIL;
               break;
           }
       }
   }
}

#if defined(R5F) && defined(SYSBIOS)
void Tx_Timer_task()
{
    UART_printf("TASK SLEEP APPROACH \n");
    uint32_t timePeriodInMilliSec = 33;  //3 sec
    SemaphoreP_Params semParams;

    SemaphoreP_Params_init(&semParams);
    semParams.mode = SemaphoreP_Mode_COUNTING;
    TxgSyncSem = SemaphoreP_create(0U, &semParams);

    while(1)
    {
        //UART_printf("\n TX ................\n");
        Txtest();
        //UART_printf("\n RX ................\n");
        Rxtest();
        UART_printf("\n Task_sleep ................\n");

        Task_sleep(timePeriodInMilliSec);
    }
}

static void Rxtest()
{
    int32_t              testStatus = CSL_PASS;
    MCAN_ErrCntStatus    errCounter;
    MCAN_ProtocolStatus protStatus;
    uint32_t    readBuffNum, loopCnt;
    MCAN_RxFIFOStatus fifoStatus;

    readBuffNum = 0U;
    loopCnt++;

    SemaphoreP_pend(RxgSyncSem, SemaphoreP_WAIT_FOREVER);

    if(((gMcanIsrIntr1Status & MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ==
                                MCAN_INTR_SRC_RX_FIFO0_NEW_MSG))
    {
        fifoStatus.num = (uint32_t)MCAN_RX_FIFO_NUM_0;
    }
    else
    {
        fifoStatus.num = (uint32_t)MCAN_RX_FIFO_NUM_1;
    }

    MCAN_getRxFIFOStatus(APP_MCAN2_BASEADDR, &fifoStatus);
    MCAN_readMsgRam(APP_MCAN2_BASEADDR,
                    MCAN_MEM_TYPE_FIFO,
                    fifoStatus.getIdx,
                    (uint32_t)fifoStatus.num,
                    &rxMsg);
    (void) MCAN_writeRxFIFOAck(APP_MCAN2_BASEADDR,
                               (uint32_t)fifoStatus.num,
                               fifoStatus.getIdx);

    MCAN_getProtocolStatus(APP_MCAN2_BASEADDR, &protStatus);

   /* Checking for Errors */
   if (((MCAN_ERR_CODE_NO_ERROR == protStatus.lastErrCode) ||
        (MCAN_ERR_CODE_NO_CHANGE == protStatus.lastErrCode)) &&
       ((MCAN_ERR_CODE_NO_ERROR == protStatus.dlec) ||
        (MCAN_ERR_CODE_NO_CHANGE == protStatus.dlec)) &&
       (0U == protStatus.pxe))
   {
//       UART_printf("\n(%dth) Message successfully received.%d , %d, %d ,%d \n",
//                   rxMsg.id,rxMsg.data[0],rxMsg.data[1],rxMsg.data[2],rxMsg.data[3]);
   }
   else
   {
       UART_printf("\nError in reception (%dth) message.\n",
                  loopCnt);
   }
}
void Rx_Timer_task()
{
    int32_t status = CSL_PASS;

    Board_pinmuxUpdate(gCockpitDemoPinmuxDataInfo,
                       BOARD_SOC_DOMAIN_MAIN);

    /* Set drive strength */
    CSL_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE +
            CSL_WKUP_CTRL_MMR_CFG0_H_IO_DRVSTRNGTH0_PROXY, 0xFU);

    CSL_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE +
            CSL_WKUP_CTRL_MMR_CFG0_V_IO_DRVSTRNGTH0_PROXY, 0xFU);

    SET_DEVICE_STATE(TISCI_DEV_MCAN2,
            TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
            status);

    SemaphoreP_Params semParams;

    SemaphoreP_Params_init(&semParams);
    semParams.mode = SemaphoreP_Mode_COUNTING;
    RxgSyncSem = SemaphoreP_create(0U, &semParams);
}

#endif

2. Also attached log file after adding interrupt status as below:-

3007.LOG.txt

3. MCU2_1 core has main() call in path basic_demos/app_tirtos/tirtos_linux/mcu2_1/main.c Task has been created for appMain() -> appInit(), so using this task I triggered MCAN application. So in case you mean two separate tasks each for Tx , Rx. Since am currently running in while(1), so how to trigger 2 parallel tasks. For experiment purpose I tried to create 2 tasks as in below file but due to while(1) loop it kept looping in first task itself.

2084.main.c

/*
 *
 * Copyright (c) 2018 Texas Instruments Incorporated
 *
 * All rights reserved not granted herein.
 *
 * Limited License.
 *
 * Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
 * license under copyrights and patents it now or hereafter owns or controls to make,
 * have made, use, import, offer to sell and sell ("Utilize") this software subject to the
 * terms herein.  With respect to the foregoing patent license, such license is granted
 * solely to the extent that any such patent is necessary to Utilize the software alone.
 * The patent license shall not apply to any combinations which include this software,
 * other than combinations with devices manufactured by or for TI ("TI Devices").
 * No hardware patent is licensed hereunder.
 *
 * Redistributions must preserve existing copyright notices and reproduce this license
 * (including the above copyright notice and the disclaimer and (if applicable) source
 * code license limitations below) in the documentation and/or other materials provided
 * with the distribution
 *
 * Redistribution and use in binary form, without modification, are permitted provided
 * that the following conditions are met:
 *
 * *       No reverse engineering, decompilation, or disassembly of this software is
 * permitted with respect to any software provided in binary form.
 *
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 *
 * *       Nothing shall obligate TI to provide you with source code for the software
 * licensed and provided to you in object code.
 *
 * If software source code is provided to you, modification and redistribution of the
 * source code are permitted provided that the following conditions are met:
 *
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 * works, are licensed by TI for use only with TI Devices.
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 * and any resulting derivative works, are licensed by TI for use only with TI Devices.
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 *
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#include <app.h>
#include <utils/console_io/include/app_log.h>
#include <stdio.h>
#include <string.h>
#include <xdc/runtime/Error.h>
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Task.h>
#include <app_ipc_rsctable.h>

static Void TxMain(UArg arg0, UArg arg1)
{
    while(1)
    {
        printf("Txmain\n");
    }
}

static Void RxMain(UArg arg0, UArg arg1)
{
    while(1)
    {
        printf("RXmain\n");
    }

}

static Void appMain(UArg arg0, UArg arg1)
{
    appInit();
    appRun();
    #if 1
    while(1)
    {
        appLogWaitMsecs(100u);
    }
    #else
    appDeInit();
    #endif
}

void StartupEmulatorWaitFxn (void)
{
    volatile uint32_t enableDebug = 0;
    do
    {
    }while (enableDebug);
}

static uint8_t gTskStackMain[8*1024]
__attribute__ ((section(".bss:taskStackSection")))
__attribute__ ((aligned(8192)))
    ;
static uint8_t gTskTxStackMain[8*1024]
__attribute__ ((section(".bss:taskStackSection")))
__attribute__ ((aligned(8192)))
    ;
static uint8_t gTskRxStackMain[8*1024]
__attribute__ ((section(".bss:taskStackSection")))
__attribute__ ((aligned(8192)))
    ;
int main(void)
{
    Task_Params tskParams;
    Error_Block eb;
    Task_Handle task;

    /* This is for debug purpose - see the description of function header */
    StartupEmulatorWaitFxn();

    Error_init(&eb);
    Task_Params_init(&tskParams);

    tskParams.arg0 = (UArg) NULL;
    tskParams.arg1 = (UArg) NULL;
    tskParams.priority = 8u;
    tskParams.stack = gTskStackMain;
    tskParams.stackSize = sizeof (gTskStackMain);
    task = Task_create(appMain, &tskParams, &eb);

    //////////////////////////////////////////////////
    Task_Params tskParams1;
    Task_Params_init(&tskParams1);

    tskParams1.arg0 = (UArg) NULL;
    tskParams1.arg1 = (UArg) NULL;
    tskParams1.priority = 8u;
    tskParams1.stack = gTskTxStackMain;
    tskParams1.stackSize = sizeof (gTskTxStackMain);
    Task_create(TxMain, &tskParams1, NULL);

    Task_Params tskParams2;
    Task_Params_init(&tskParams2);

    tskParams2.arg0 = (UArg) NULL;
    tskParams2.arg1 = (UArg) NULL;
    tskParams2.priority = 8u;
    tskParams2.stack = gTskRxStackMain;
    tskParams2.stackSize = sizeof (gTskRxStackMain);
    Task_create(RxMain, &tskParams2, NULL);

    //////////////////////////////////////////////////
    if(NULL == task)
    {
        BIOS_exit(0);
    }
    BIOS_start();

    return 0;
}

uint32_t appGetDdrSharedHeapSize()
{
    return DDR_SHARED_MEM_SIZE;
}

Kindly suggest.

Thanks and Regards

Pooja Krishna

0 Karan Saxena over 4 years ago in reply to Pooja R1

TI__Guru* 75663 points

Hi Pooja,

-1-

You need to print the interrupt status only when it doesn't go in any of the if checks (for Tx and Rx both), else there will be a print saying "Error in Rx" everytime there is a Tx event triggering the interrupt and vice versa.

You can have something like -

static void App_mcanIntr01ISR(uintptr_t arg)
{
    uint32_t isrType = 2; //set 0 in case of Tx, 1 in case of Rx and 2 is when error interrupt

    gMcanIsrIntr1Status = MCAN_getIntrStatus(gMcanModAddr);
    MCAN_clearIntrStatus(gMcanModAddr, gMcanIsrIntr1Status);
    if (MCAN_INTR_SRC_TRANS_COMPLETE ==
        (gMcanIsrIntr1Status & MCAN_INTR_SRC_TRANS_COMPLETE))
    {
        isrType = 0;
        SemaphoreP_post(TxgSyncSem);
    }

    if(((gMcanIsrIntr1Status & MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ==
         MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ||
       ((gMcanIsrIntr1Status & MCAN_INTR_SRC_RX_FIFO1_NEW_MSG) ==
         MCAN_INTR_SRC_RX_FIFO1_NEW_MSG))
    {
        isrType = 1;
        SemaphoreP_post(RxgSyncSem);
    }

    if(isrType == 3)
    {
        UART_printf("ERROR ISR, Interrupt Status: 0x%x\n", gMcanIsrIntr1Status);
    }
}

Even without that I was trying to get an idea of what errors were being generated and it seems like you are looking messages from Rx FIFO1. But please post a reply after modifications to print only error interrupts, then we can look more closely at it.

-2-

Even in case of errors in Tx or Rx, there should not be any hang, it should just not send/receive CAN messages. If you are everywhere using semaphores then the loss of a message(s) would leave the CPU on the Semaphore pend and then the task gets blocked and the other tasks keep on running. Can you please elaborate on that? Does the vision app still runs and just the CAN tx/rx stops without hampering the other task?

-3-

static Void TxMain(UArg arg0, UArg arg1)
{
    while(1)
    {
        printf("Txmain\n");
        // some instruction which relinquishes CPU
    }
}

static Void RxMain(UArg arg0, UArg arg1)
{
    while(1)
    {
        printf("RXmain\n");
        // some instruction which relinquishes CPU
    }
}

When you have something like this, then whichever task gets scheduled first will hog the CPU as there is no time when the CPU goes to the idle task and the scheduler runs again. But this will not be the case in more practical case. We should always try to relinquish control of the CPU in the task, so in the case when you will have a Tx task and an Rx task, you will have some kind of task sleep (in Tx) and also a semaphore pend (in both Tx and Rx).

Upon execution of a task sleep or a pend operation the CPU will become idle and the scheduler will run and schedule the other task in the scheduler's ready queue (these will be the tasks ready to execute and not blocked on any resource).

Even in you dummy example of two tasks you can add a task sleep in the while(1) after the print and you will see alternate prints of Tx and Rx. The priority of the tasks will also matter, but to start with you can keep both tasks at the same priority.

You can look at the SYSBIOS documentation for more details on such things.

Regards,

Karan

0 Pooja R1 over 4 years ago in reply to Karan Saxena

Intellectual 790 points

Hi Karan,

1. As suggested modifications were done in ISR to dump the error status as below:- mcan_log_14apr.txt

2. Am able to run dl demo application ( ./run_app_tidl.sh ) even if asynchronous Tx , Rx hangs.

3. Upon adding Task_sleep(33) in both Rxmain and Txmain, it started happening alternatively with same priority. Later I observed that TX hangs but Rx keeps happening.

But as per my requirement if I remove the time period of RX , its stuck inside Rxmain. Does it mean I may have to keep minimum Task_sleep of atleast 1ms to give some idle time to perform task switch.

Observed the same hanging of Tx happening even if its parallel tasks or sequential triggering of Rx, Tx.

Thanks and Regards

Pooja

0 Karan Saxena over 4 years ago in reply to Pooja R1

TI__Guru* 75663 points

Hi Pooja,

-1-

One quick feedback - you need not have any Task_sleep(33) in the RxMain().

The semaphore pend in the Rxtest() will ensure that the task doesn't hog the CPU and gives time to the Tx task. (as when you are pending on a semaphore the CPU will be free and this will give the other task a chance to run)

-2-

Interrupt status (0x80 - means that the 7th bit is 1) shows that you are loosing messages in RX FIFO 1. Either you are receiving the messages at a higher rate and not draining them at the same rate (which could be possible if you are receiving messages at an interval less than 33ms, as you had your Rx task running at 33ms - remove that and we can check again).

The interrupt status doesn't show any Tx error. How do you confirm that Tx is not happening? Have you connected some CAN emulator?

- I would expect (based on the interrupt status) that the Rx will not be happening because in the FIFO1 messages are being lost. Please do confirm, that TX indeed is not happening. (if possible connect an external CAN emulator to do so).

-3-

One problem I see in your code is that you should not be doing things like enabling transmission interrupt for buffer 1 again and again. So better way of having your Tx and Rx task will be to have something like this-

/* Please refer this type of pseudo code */

static Void TxMain(UArg arg0, UArg arg1)
{
    print("Tx thread\n");
    Txtest();
}

static Void RxMain(UArg arg0, UArg arg1)
{
    print("Rx thread\n");
    Rxtest();
}

static void Txtest()
{
    //All one time configurations and everything that need not be called again and again
    //Example add the Tx interrupt configuration etc. code here, also if all the signal copy code isn't needed in a loop move that here too.

    while(1)
    {
        //only code that needs to be run periodically.
        //this should be the MCAN_writeMsgRam(), MCAN_txBufAddReq(), SemaphoreP_pend etc.
        
        Task_sleep(time_interval);  //<-- this will make this task periodic
    }
}

static void Rxtest()
{
    //same idea as the Tx task, add code which needs to be executed in loop in the while(1) rest should happen only once.
    //here no need for a task sleep as this task should is triggered by the isr post of the semaphore

    while(1)
    {
        SemaphoreP_pend();

        //read the message
    }
}

Regards,
Karan

0 Pooja R1 over 4 years ago in reply to Karan Saxena

Intellectual 790 points

Hi Karan,

1. As suggested , removed task_sleep from RX test and also changed code of Txtest() not to iterate enabling transmission interrupt.But data copy needs to happen inside loop since as of now its dummy data later I need to fetch from A72 core via dl demo application.

2. Observed that upon adding UART_printf statements for Rxtest() and Txtest() after checking for Errors, Tx and Rx started running properly. But once I remove these 2 prints , application did not even work for one iteration.

3. I observe Tx happens or not by observing the below messages and its time stamp as below in Trace window:-

Kindly let me know the reason for this behavior with / without print.

8713.app_mcan2.c

/*
 *   Copyright (c) Texas Instruments Incorporated 2016-2019
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

/**
 *  \file     app_mcan2.c
 *
 *  \brief    This file contains MCAN sample code.
 *
 *  \details  MCAN operational mode is set to Classic CAN.
 *
 */

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
#define TIMER_CALL

#include <stdint.h>
#include <stdio.h>
#include <ti/csl/csl_types.h>
#include <ti/csl/soc.h>
#include <ti/csl/hw_types.h>
#include <ti/csl/arch/csl_arch.h>
#include <ti/csl/csl_mcan.h>
#include <ti/drv/uart/UART.h>
#include <ti/drv/uart/UART_stdio.h>
#include <ti/osal/osal.h>
#include <ti/drv/gpio/GPIO.h>
#include <ti/drv/gpio/soc/GPIO_soc.h>
#include <ti/csl/csl_gpio.h>
#include <ti/board/board.h>
#include <ti/drv/i2c/I2C.h>
#if defined (SOC_J721E)
#include <ti/drv/sciclient/sciclient.h>
#endif
#include <utils/mcan/app_mcan2.h>
#include <utils/remote_service/include/app_remote_service.h>
#include <utils/console_io/include/app_log.h>

#include <ti/drv/ipc/ipc.h>
#include <ti/osal/SemaphoreP.h>
#include "app_CAN_reader.h"
#include "app_sciclient_helper.h"
#include <ti/sysbios/knl/Task.h>

#include <ti/board/src/j721e_evm/include/board_cfg.h>
#include <ti/board/src/j721e_evm/include/board_pinmux.h>
#include <ti/csl/soc/cslr_soc_ctrl_mmr.h>
#ifdef TIMER_CALL
#include <ti/sysbios/timers/dmtimer/Timer.h>
#include <ti/osal/TimerP.h>
#include <ti/drv/uart/UART_stdio.h>
#include <ti/drv/uart/UART.h>

Timer_Handle timerHandle;

static uint32_t gMcanTask = 1U;
void (*fp_taskFxn)();
volatile uint32_t debugVar = 1U;
uint32_t numTimerTaskHit = 0;
#endif
static uint8_t gTskTxStackMain[8*1024]
__attribute__ ((section(".bss:taskStackSection")))
__attribute__ ((aligned(8192)))
    ;
static uint8_t gTskRxStackMain[8*1024]
__attribute__ ((section(".bss:taskStackSection")))
__attribute__ ((aligned(8192)));
/* ========================================================================== */
/*                                Macros                                      */
/* ========================================================================== */
#if defined (SOC_AM65XX)
#define APP_ENABLE_UART_PRINT                    (1U)
#elif defined (SOC_J721E)
#define APP_ENABLE_UART_PRINT                    (1U)
#endif

#define APP_MCAN_STD_ID_FILT_START_ADDR          (0U)
#define APP_MCAN_STD_ID_FILTER_NUM               (1U)
#define APP_MCAN_EXT_ID_FILT_START_ADDR          (48U)
#define APP_MCAN_EXT_ID_FILTER_NUM               (1U)
#define APP_MCAN_TX_EVENT_START_ADDR             (100U)
#define APP_MCAN_TX_EVENT_SIZE                   (5U)
#define APP_MCAN_TX_BUFF_START_ADDR              (148U)
#define APP_MCAN_TX_BUFF_SIZE                    (5U)
#define APP_MCAN_TX_FIFO_SIZE                    (5U)
#define APP_MCAN_FIFO_0_START_ADDR               (548U)
#define APP_MCAN_FIFO_0_NUM                      (5U)
#define APP_MCAN_FIFO_1_START_ADDR               (748U)
#define APP_MCAN_FIFO_1_NUM                      (5U)
#define APP_MCAN_RX_BUFF_START_ADDR              (948U)

#define APP_MCAN_EXT_ID_AND_MASK                 (0x1FFFFFFFU)

#define APP_MCU_MCAN_0_INT0                                   (0U)
#define APP_MCU_MCAN_0_INT1                                   (1U)
#define APP_MCU_MCAN_0_TS_INT                                 (4U)
#define APP_MCU_MCAN_1_INT0                                   (2U)
#define APP_MCU_MCAN_1_INT1                                   (3U)
#define APP_MCU_MCAN_1_TS_INT                                 (5U)

#define I2C_BUS_NUM                     (0)
#define TCA6424_SLAVE_ADDR              ((uint8_t) 0x23U)

#define TCA6424_CMD_AUTO_INC            ((uint8_t) 0x80U)

#if defined (SOC_J721E)
#if defined (BUILD_MCU1_0)
#define APP_MAIN_MCAN_2_INT0                (CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0)
#define APP_MAIN_MCAN_2_INT1                (CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_1)
#define APP_MAIN_MCAN_2_TS_INT              (CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_2)
#else
#define APP_MAIN_MCAN_0_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN0_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_0_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN0_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_0_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_2_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN2_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_2_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN2_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_2_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN2_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_4_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN4_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_4_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN4_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_4_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN4_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_5_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN5_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_5_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN5_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_5_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN5_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_6_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN6_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_6_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN6_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_6_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN6_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_7_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN7_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_7_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN7_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_7_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN7_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_9_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN9_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_9_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN9_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_9_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN9_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_11_INT0               (CSLR_R5FSS1_CORE0_INTR_MCAN11_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_11_INT1               (CSLR_R5FSS1_CORE0_INTR_MCAN11_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_11_TS_INT             (CSLR_R5FSS1_CORE0_INTR_MCAN11_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#endif
#endif

/* Print buffer character limit for prints- UART or CCS Console */
#define APP_PRINT_BUFFER_SIZE                       (4000)
#if defined (SOC_AM65XX)
/* Port and pin number mask for GPIO Load pin.
   Bits 7-0: Pin number  and Bits 15-8: Port number */
#define AM65XX_IDK_GPIO_CAN0_STB_PIN    (0x012F)
#define AM65XX_IDK_GPIO_CAN1_STB_PIN    (0x0143)
#endif
#if defined (SOC_J721E)
#define J721E_GPIO_GESI_CAN_STB_PIN     (0x003C)
#define J721E_GPIO_MAIN_MCAN2_STB_PIN   (0x007F)
#endif
/*****************************/
/*****************************/
#define TX_CODE 0
#define RX_CODE 0
#define TX_RX_CODE 1

volatile uint32_t gMcanIsrIntr1Status;
/*****************************/
/*****************************/
/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */
#define APP_USE_CAN
#if defined (APP_USE_CAN)
static pinmuxPerCfg_t gMcan2PinCfg[] =
{
    /* MyMCAN2 -> MCAN2_RX -> AC2 */
    {
        PIN_UART0_CTSN, PIN_MODE(3) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCAN2 -> MCAN2_TX -> AB1 */
    {
        PIN_UART0_RTSN, PIN_MODE(3) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gI2c0PinCfg[] =
{
    /* MyI2C0 -> I2C0_SCL -> AC5 */
    {
        PIN_I2C0_SCL, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    /* MyI2C0 -> I2C0_SDA -> AA5 */
    {
        PIN_I2C0_SDA, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gGpio0PinCfg[] =
{
    /* MyGPIO0 -> GPIO0_127 -> AC4 */
    {
        PIN_UART1_CTSN, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gMcanPinCfg[] =
{
    {0, TRUE, gMcan2PinCfg},
    {1, TRUE, gI2c0PinCfg},
    {2, TRUE, gGpio0PinCfg},
    {PINMUX_END}
};
#endif

static pinmuxBoardCfg_t gCockpitDemoPinmuxDataInfo[] =
{
#if defined (APP_USE_CAN)
    {1, gMcanPinCfg},
#endif
    {PINMUX_END}
};

uint32_t          gMcanAppdataSize[16] =
{0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
volatile uint32_t gMcanIsrIntr0Flag = 1U;
//volatile uint32_t gMcanIsrIntr1Flag = 1U;
SemaphoreP_Handle RxgSyncSem;
SemaphoreP_Handle TxgSyncSem;
MCAN_ECCErrStatus gMcaneccErr;
#define APP_MCAN2_BASEADDR                       (CSL_MCAN2_MSGMEM_RAM_BASE)
uint32_t gMcanModAddr = APP_MCAN2_BASEADDR;

MCAN_TxBufElement          txMsg;
MCAN_RxBufElement    rxMsg;
MCAN_MsgRAMConfigParams    msgRAMConfigParams;
MCAN_ConfigParams          configParams;

const uint32_t mcan2TxMsgId[] = {OBJ_MSG_ID1,OBJ_MSG_ID2,OBJ_MSG_ID3,OBJ_MSG_ID4,OBJ_MSG_ID5,OBJ_MSG_ID6,OBJ_MSG_ID7,OBJ_MSG_ID8,OBJ_MSG_ID9,OBJ_MSG_ID10,OBJ_MSG_ID11,OBJ_MSG_ID12,OBJ_MSG_ID13,OBJ_MSG_ID14,OBJ_MSG_ID15,OBJ_MSG_ID16,OBJ_MSG_ID17,OBJ_MSG_ID18,OBJ_MSG_ID19,OBJ_MSG_ID20,\
                                 OBJ_MSG_ID21,OBJ_MSG_ID22,OBJ_MSG_ID23,OBJ_MSG_ID24,OBJ_MSG_ID25,OBJ_MSG_ID26,OBJ_MSG_ID27,OBJ_MSG_ID28,OBJ_MSG_ID29,OBJ_MSG_ID30,OBJ_MSG_ID31,OBJ_MSG_ID32,OBJ_MSG_ID33,OBJ_MSG_ID34,OBJ_MSG_ID35,OBJ_MSG_ID36,OBJ_MSG_ID37,OBJ_MSG_ID38,OBJ_MSG_ID39,\
                                 OBJ_MSG_ID40,OBJ_MSG_ID41
};



#if defined (SOC_J721E)
/* GPIO Driver board specific pin configuration structure */
GPIO_PinConfig gpioPinConfigs[] = {
    /* Output pin : CAN STB */
    J721E_GPIO_GESI_CAN_STB_PIN   | GPIO_CFG_OUTPUT,
    J721E_GPIO_MAIN_MCAN2_STB_PIN | GPIO_CFG_OUTPUT,
};
#endif

/* GPIO Driver call back functions */
GPIO_CallbackFxn gpioCallbackFunctions[] = {
    NULL
};

/* GPIO Driver configuration structure */
GPIO_v0_Config GPIO_v0_config = {
        gpioPinConfigs,
        gpioCallbackFunctions,
        sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
        sizeof(gpioCallbackFunctions) / sizeof(GPIO_CallbackFxn),
        0,
    };
/* ========================================================================== */
/*                 Internal Function Declarations                             */
/* ========================================================================== */

/**
 * \brief   This function will configure MCAN module
 *
 * \param   none.
 *
 * \retval  status      configuration status.
 */
static int32_t App_mcanConfig(void);

int32_t appRemoteServiceMCAN2Handler(char *service_name, uint32_t cmd,
    void *prm, uint32_t prm_size, uint32_t flags);
/**
 * \brief   This function will configure X-BAR for MCAN interrupts
 *
 * \param   none.
 *
 * \retval  status      configuration status.
 */
static int32_t App_mcanXBarConfig(void);

/**
 * \brief   This is Interrupt Service Routine for MCAN interrupt 0.
 *
 * \param   none.
 *
 * \retval  none.
 */
static void App_mcanIntr01ISR(uintptr_t arg);
/**
 * \brief   This API will load the register from ECC memory bank.
 *
 * \param   txMsg           message object to be transmitted.
 *
 * \return  None.
 */
static int32_t App_mcanRegisterInterrupt(uint32_t intNum, void f(uintptr_t));

/* ========================================================================== */
/*                          Function Definitions                              */
/* ========================================================================== */
#define TCA6424_CMD_AUTO_INC            ((uint8_t) 0x80U)

/* Input status register */
#define TCA6424_REG_INPUT0              ((UInt8) 0x00U)
#define TCA6424_REG_INPUT1              ((UInt8) 0x01U)
#define TCA6424_REG_INPUT2              ((UInt8) 0x02U)

/* Output register to change state of output BIT set to 1, output set HIGH */
#define TCA6424_REG_OUTPUT0             ((uint8_t) 0x04U)
#define TCA6424_REG_OUTPUT1             ((uint8_t) 0x05U)
#define TCA6424_REG_OUTPUT2             ((uint8_t) 0x06U)

/* Configuration register. BIT = '1' sets port to input, BIT = '0' sets
 * port to output */
#define TCA6424_REG_CONFIG0             ((uint8_t) 0x0CU)
#define TCA6424_REG_CONFIG1             ((uint8_t) 0x0DU)
#define TCA6424_REG_CONFIG2             ((uint8_t) 0x0EU)



void SetupI2CTransfer(I2C_Handle handle,  uint32_t slaveAddr,
                      uint8_t *writeData, uint32_t numWriteBytes,
                      uint8_t *readData,  uint32_t numReadBytes)
{
    bool status;
    I2C_Transaction i2cTransaction;

    I2C_transactionInit(&i2cTransaction);
    i2cTransaction.slaveAddress = slaveAddr;
    i2cTransaction.writeBuf = (uint8_t *)&writeData[0];
    i2cTransaction.writeCount = numWriteBytes;
    i2cTransaction.readBuf = (uint8_t *)&readData[0];
    i2cTransaction.readCount = numReadBytes;
    status = I2C_transfer(handle, &i2cTransaction);
    if(FALSE == status)
    {
        UART_printf("\n Data Transfer failed. \n");
    }
}

void padConfig_prcmEnable()
{
    /* UART Init */
    Board_initCfg   boardCfg;
    Board_STATUS    boardStatus;

#if defined (SOC_J721E)
    I2C_Params      i2cParams;
    I2C_Handle      handle = NULL;
    uint8_t         dataToSlave[4];
#endif

    boardCfg = BOARD_INIT_MODULE_CLOCK |
               BOARD_INIT_PINMUX_CONFIG;
#if (APP_ENABLE_UART_PRINT == 1)
    boardCfg |= BOARD_INIT_UART_STDIO;
#endif
    boardStatus = Board_init(boardCfg);
    if (boardStatus != BOARD_SOK)
    {
        UART_printf("[Error] Board init failed!!\n");
    }

    /* Pin mux for CAN STB used in GESI board */
    *(volatile unsigned int *)(0x0011c0f4) = 0x20007;
    /* Pinmux for MAIN_MCAN4 */
    *(volatile unsigned int *)(0x0011c020) = 0x60006;
    *(volatile unsigned int *)(0x0011c024) = 0x60006;
    /* Pinmux for MAIN_MCAN5 */
    *(volatile unsigned int *)(0x0011c04c) = 0x60006;
    *(volatile unsigned int *)(0x0011c050) = 0x60006;
    /* Pinmux for MAIN_MCAN6 */
    *(volatile unsigned int *)(0x0011c054) = 0x60006;
    *(volatile unsigned int *)(0x0011c06C) = 0x60006;
    /* Pinmux for MAIN_MCAN7 */
    *(volatile unsigned int *)(0x0011c074) = 0x60006;
    *(volatile unsigned int *)(0x0011c078) = 0x60006;
    /* Pinmux for MAIN_MCAN9 */
    *(volatile unsigned int *)(0x0011c0cc) = 0x60006;
    *(volatile unsigned int *)(0x0011c0d0) = 0x60006;
    /* Pinmux for MAIN_MCAN11 */
    *(volatile unsigned int *)(0x0011c11c) = 0x60006;
    *(volatile unsigned int *)(0x0011c120) = 0x60006;

    /* GPIO initialization */
    GPIO_init();

    /* Enable CAN transceivers by setting the STB pins */
#if defined (SOC_AM65XX)
    GPIO_write(0, GPIO_PIN_HIGH);
    GPIO_write(1, GPIO_PIN_HIGH);
#elif defined (SOC_J721E)
    /* Enable the TCAN on GESI board.
     * Main Domain MCAN instances 4,5,6,7,9,11.
     */
    GPIO_write(0, GPIO_PIN_LOW);

    /* Enable MCU MCAN 1, WKUP_GPIO0_2. */
    GPIOSetDirMode_v0(CSL_WKUP_GPIO0_BASE, 2, GPIO_DIRECTION_OUTPUT);
    GPIOPinWrite_v0(CSL_WKUP_GPIO0_BASE, 2, GPIO_PIN_LOW);

    /* Enable MCU MCAN 0, WKUP_GPIO0_0, WKUP_GPIO0_54 */
    GPIOSetDirMode_v0(CSL_WKUP_GPIO0_BASE, 0, GPIO_DIRECTION_OUTPUT);
    GPIOPinWrite_v0(CSL_WKUP_GPIO0_BASE, 0, GPIO_PIN_HIGH);
    GPIOSetDirMode_v0(CSL_WKUP_GPIO0_BASE, 54, GPIO_DIRECTION_OUTPUT);
    GPIOPinWrite_v0(CSL_WKUP_GPIO0_BASE, 54, GPIO_PIN_HIGH);

    /* Enable Main MCAN 2, GPIO0_127. */
    GPIO_write(1, GPIO_PIN_LOW);

    /*
     * Configuring TCA6424 IO Exp 2 with addr 0x22
     * This io expander is controlled by i2c0
     * For Main MCAN2 P13 and P14 should be set to 0, This should route the MCAN2 STB line to transciver.
     * For Main MCAN0 P06 and P07 should be set to 1.
     */
    /* I2C initialization */
    I2C_init();
    I2C_Params_init(&i2cParams);
    i2cParams.transferMode = I2C_MODE_BLOCKING;
    i2cParams.bitRate = I2C_400kHz;
    i2cParams.transferCallbackFxn = NULL;

    handle = I2C_open(0U, &i2cParams);
    printf("I2C_open .........\n");

    dataToSlave[0] = TCA6424_REG_CONFIG0 | TCA6424_CMD_AUTO_INC;
    dataToSlave[1] = 0x0U;
    SetupI2CTransfer(handle, 0x23, &dataToSlave[0], 2, NULL, 0);
    printf("SetupI2CTransfer .........\n");

    dataToSlave[0] = TCA6424_REG_INPUT0 | TCA6424_CMD_AUTO_INC;
    dataToSlave[1] = 0x0U;
    dataToSlave[2] = 0x0U;
    dataToSlave[3] = 0x0U;
    SetupI2CTransfer(handle, 0x23, &dataToSlave[0], 1, &dataToSlave[1], 3);

    /* Set P06 and P07 to 1.
     * Set P13 and P14 to 0.
     */
    dataToSlave[0] = TCA6424_REG_OUTPUT0 | TCA6424_CMD_AUTO_INC;
    dataToSlave[1] |= 0xC0;
    dataToSlave[2] &= ~(0x18);
    SetupI2CTransfer(handle, 0x23, &dataToSlave[0], 1, &dataToSlave[1], 3);
#endif
}
#if defined(R5F) && defined(SYSBIOS)
int32_t appMcan2Init(void)
{
    int32_t                    configStatus = CSL_PASS;
    uint32_t                  /* mode         = 0U, */loopCnt = 0U;

    /* Do Pad Config for UART and MCAN */
    padConfig_prcmEnable();

    UART_printf("\n START MCAN2 INIT....\n");

    /* CrossBar Configuration */
    configStatus = App_mcanXBarConfig();

    /* Initialize message to transmit */
    txMsg.id  = (uint32_t)((uint32_t)(0x4U) << 18U);
    txMsg.rtr = 0U;
    txMsg.xtd = 0U;
    txMsg.esi = 0U;
    txMsg.dlc = 0xFU;
    txMsg.brs = 1U;
    txMsg.fdf = 0u;//1U;
    txMsg.efc = 1U;
    txMsg.mm  = 0xAAU;
    for (loopCnt = 0; loopCnt < MCAN_MAX_PAYLOAD_BYTES; loopCnt++)
    {
        txMsg.data[loopCnt] = 0;
    }
    configStatus = App_mcanConfig();
    //int status = appRemoteServiceMcan2Init();

    Rx_Timer_task();
    Tx_Timer_task();

    UART_printf("\n MCAN2 INIT END..........\n");

    return 0;
}
#endif

/* ========================================================================== */
/*                 Internal Function Definitions                              */
/* ========================================================================== */
static int32_t App_mcanRegisterInterrupt(uint32_t intNum, void f(uintptr_t))
{
    int32_t configStatus = STW_SOK;
    OsalRegisterIntrParams_t    intrPrms;
    OsalInterruptRetCode_e      osalRetVal;
    HwiP_Handle                 hwiHandle = NULL;

    /* Enable CPU Interrupts and register ISR - MCAN0 Intr0 */
    Osal_RegisterInterrupt_initParams(&intrPrms);
    /* Populate the interrupt parameters */
    intrPrms.corepacConfig.arg              = (uintptr_t) NULL;
    intrPrms.corepacConfig.isrRoutine       = f;
    intrPrms.corepacConfig.priority         = 0U;
    intrPrms.corepacConfig.corepacEventNum  = 0U;
    intrPrms.corepacConfig.intVecNum        = intNum;

    /* Register interrupts */
    osalRetVal = Osal_RegisterInterrupt(&intrPrms, &hwiHandle);
    if(OSAL_INT_SUCCESS != osalRetVal)
    {
        configStatus = CSL_EFAIL;
    }
    return configStatus;
}

static int32_t App_mcanXBarConfig(void)
{
    int32_t configStatus = STW_SOK;
    /* Main MCAN Inst 2 */
#if TX_CODE
    configStatus =  App_mcanRegisterInterrupt(APP_MAIN_MCAN_2_INT0, &App_mcanIntr0ISR);
#elif RX_CODE
    configStatus = App_mcanRegisterInterrupt (APP_MAIN_MCAN_2_INT1, &App_mcanIntr1ISR);
#else
    configStatus = App_mcanRegisterInterrupt (APP_MAIN_MCAN_2_INT0, &App_mcanIntr01ISR);
#endif
    if(STW_SOK != configStatus)
    {
        UART_printf("CrossBar/Interrupt Configuration failed.\n");
    }
    else
    {
        UART_printf("CrossBar/Interrupt Configuration done.\n");
    }

    return configStatus;
}

static int32_t App_mcanConfig(void)
{
    uint32_t                   fdoe;
    int32_t                    configStatus = CSL_PASS;
    MCAN_RevisionId            revId;
    MCAN_InitParams            initParams;
    MCAN_StdMsgIDFilterElement stdFiltelem;
    MCAN_BitTimingParams       bitTimes;

    /* Initialize MCAN Init params */
#ifdef MCAN_500KBPS
    initParams.fdMode          = 0x0U;
#else
    initParams.fdMode          = 0x1U;
#endif
    initParams.brsEnable       = 0x1U;
    initParams.txpEnable       = 0x0U;
    initParams.efbi            = 0x0U;
    initParams.pxhddisable     = 0x0U;
    initParams.darEnable       = 0x1U;
    initParams.wkupReqEnable   = 0x1U;
    initParams.autoWkupEnable  = 0x1U;
    initParams.emulationEnable = 0x1U;
    initParams.emulationFAck   = 0x0U;
    initParams.clkStopFAck     = 0x0U;
    initParams.wdcPreload      = 0xFFU;
    initParams.tdcEnable       = 0x1U;
    initParams.tdcConfig.tdcf  = 0xAU;
    initParams.tdcConfig.tdco  = 0x6U;
    /* Initialize MCAN Config params */
    configParams.monEnable         = 0x0U;
    configParams.asmEnable         = 0x0U;
    configParams.tsPrescalar       = 0xFU;
    configParams.tsSelect          = 0x0U;
    configParams.timeoutSelect     = MCAN_TIMEOUT_SELECT_CONT;
    configParams.timeoutPreload    = 0xFFFFU;
    configParams.timeoutCntEnable  = 0x0U;
    configParams.filterConfig.rrfs = 0x1U;
    configParams.filterConfig.rrfe = 0x1U;
    configParams.filterConfig.anfe = 0x1U;
    configParams.filterConfig.anfs = 0x1U;
    /* Initialize Message RAM Sections Configuration Parameters */
    msgRAMConfigParams.flssa                = APP_MCAN_STD_ID_FILT_START_ADDR;
    msgRAMConfigParams.lss                  = APP_MCAN_STD_ID_FILTER_NUM;
    msgRAMConfigParams.flesa                = APP_MCAN_EXT_ID_FILT_START_ADDR;
    msgRAMConfigParams.lse                  = APP_MCAN_EXT_ID_FILTER_NUM;
    msgRAMConfigParams.txStartAddr          = APP_MCAN_TX_BUFF_START_ADDR;
    msgRAMConfigParams.txBufNum             = APP_MCAN_TX_BUFF_SIZE;
    msgRAMConfigParams.txFIFOSize           = 0U;
    msgRAMConfigParams.txBufMode            = 0U;
    msgRAMConfigParams.txBufElemSize        = MCAN_ELEM_SIZE_64BYTES;
    msgRAMConfigParams.txEventFIFOStartAddr = APP_MCAN_TX_EVENT_START_ADDR;
    msgRAMConfigParams.txEventFIFOSize      = APP_MCAN_TX_BUFF_SIZE;
    msgRAMConfigParams.txEventFIFOWaterMark = 3U;
    msgRAMConfigParams.rxFIFO0startAddr     = APP_MCAN_FIFO_0_START_ADDR;
    msgRAMConfigParams.rxFIFO0size          = APP_MCAN_FIFO_0_NUM;
    msgRAMConfigParams.rxFIFO0waterMark     = 3U;
    msgRAMConfigParams.rxFIFO0OpMode        = 0U;
    msgRAMConfigParams.rxFIFO1startAddr     = APP_MCAN_FIFO_1_START_ADDR;
    msgRAMConfigParams.rxFIFO1size          = APP_MCAN_FIFO_1_NUM;
    msgRAMConfigParams.rxFIFO1waterMark     = 3U;
    msgRAMConfigParams.rxFIFO1OpMode        = 0U;
    msgRAMConfigParams.rxBufStartAddr       = APP_MCAN_RX_BUFF_START_ADDR;
    msgRAMConfigParams.rxBufElemSize        = MCAN_ELEM_SIZE_64BYTES;
    msgRAMConfigParams.rxFIFO0ElemSize      = MCAN_ELEM_SIZE_64BYTES;
    msgRAMConfigParams.rxFIFO1ElemSize      = MCAN_ELEM_SIZE_64BYTES;
    /* Initialize Tx Buffer Config params */
    stdFiltelem.sfid2 = 0x0U;
    stdFiltelem.sfid1 = 0x0U;;//0x4U;
    stdFiltelem.sfec  = 0x0U;;//0x7U;
    stdFiltelem.sft   = 0x0U;
    /* Initialize bit timings
     * Configuring 1Mbps and 5Mbps as nominal and data bit-rate respectively */
#ifdef MCAN_500KBPS
    bitTimes.nomRatePrescalar   = 0xFU;
#else
    bitTimes.nomRatePrescalar   = 0x7U;
#endif
    bitTimes.nomTimeSeg1        = 0x5U;
    bitTimes.nomTimeSeg2        = 0x2U;
    bitTimes.nomSynchJumpWidth  = 0x0U;
    bitTimes.dataRatePrescalar  = 0x1U;
    bitTimes.dataTimeSeg1       = 0x3U;
    bitTimes.dataTimeSeg2       = 0x2U;
    bitTimes.dataSynchJumpWidth = 0x0U;

    /* Get MCANSS Revision ID */
    MCAN_getRevisionId(gMcanModAddr, &revId);
    UART_printf("MCANSS Revision ID:\n");
    UART_printf("scheme:0x%x\n", revId.scheme);
    UART_printf("Business Unit:0x%x\n", revId.bu);
    UART_printf("Module ID:0x%x\n", revId.modId);
    UART_printf("RTL Revision:0x%x\n", revId.rtlRev);
    UART_printf("Major Revision:0x%x\n", revId.major);
    UART_printf("Custom Revision:0x%x\n", revId.custom);
    UART_printf("Minor Revision:0x%x\n", revId.minor);
    /* Enable Auto wakeup */
    fdoe = MCAN_isFDOpEnable(gMcanModAddr);
    if ((uint32_t)TRUE == fdoe)
    {
        UART_printf("CAN-FD operation is enabled through E-Fuse.\n");
    }
    else
    {
        UART_printf("CAN-FD operation is disabled through E-Fuse.\n");
    }
    /* wait for memory initialization to happen */
    while (FALSE == MCAN_isMemInitDone(gMcanModAddr))
    {}
    /* Get endianess value */
    UART_printf("Endianess Value: 0x%x\n",
                       MCAN_getEndianVal(gMcanModAddr));
    /* Put MCAN in SW initialization mode */
    MCAN_setOpMode(gMcanModAddr, MCAN_OPERATION_MODE_SW_INIT);
    while (MCAN_OPERATION_MODE_SW_INIT != MCAN_getOpMode(gMcanModAddr))
    {}
    /* Initialize MCAN module */
    MCAN_init(gMcanModAddr, &initParams);
    /* Configure MCAN module */
    MCAN_config(gMcanModAddr, &configParams);
    /* Configure Bit timings */
    MCAN_setBitTime(gMcanModAddr, &bitTimes);
    /* Set Extended ID Mask */
    MCAN_setExtIDAndMask(gMcanModAddr, APP_MCAN_EXT_ID_AND_MASK);
    /* Configure Message RAM Sections */
    MCAN_msgRAMConfig(gMcanModAddr, &msgRAMConfigParams);
    /* Configure Standard ID filter element */
    MCAN_addStdMsgIDFilter(gMcanModAddr, 0U, &stdFiltelem);
    /* Take MCAN out of the SW initialization mode */
    MCAN_setOpMode(gMcanModAddr, MCAN_OPERATION_MODE_NORMAL);
    while (MCAN_OPERATION_MODE_NORMAL != MCAN_getOpMode(gMcanModAddr))
    {}

    /* Enable Interrupts */
    MCAN_enableIntr(gMcanModAddr, MCAN_INTR_MASK_ALL, (uint32_t)TRUE);
    MCAN_enableIntr(gMcanModAddr,
                    MCAN_INTR_SRC_RES_ADDR_ACCESS, (uint32_t)FALSE);

    /* Select Interrupt Line */
    MCAN_selectIntrLine(APP_MCAN2_BASEADDR,
                        MCAN_INTR_MASK_ALL,
                        MCAN_INTR_LINE_NUM_0);

    /* Enable Interrupt Line */
    MCAN_enableIntrLine(APP_MCAN2_BASEADDR,
                        MCAN_INTR_LINE_NUM_0,
                        1U);
    return configStatus;
}

static void App_mcanIntr01ISR(uintptr_t arg)
{
    uint32_t isrType = 2; //set 0 in case of Tx, 1 in case of Rx and 2 is when error interrupt
    gMcanIsrIntr1Status = MCAN_getIntrStatus(gMcanModAddr);
    MCAN_clearIntrStatus(gMcanModAddr, gMcanIsrIntr1Status);
    if (MCAN_INTR_SRC_TRANS_COMPLETE ==
        (gMcanIsrIntr1Status & MCAN_INTR_SRC_TRANS_COMPLETE))
    {
        isrType = 0;
        SemaphoreP_post(TxgSyncSem);
    }

    if(((gMcanIsrIntr1Status & MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ==
         MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ||
       ((gMcanIsrIntr1Status & MCAN_INTR_SRC_RX_FIFO1_NEW_MSG) ==
         MCAN_INTR_SRC_RX_FIFO1_NEW_MSG))
    {
        isrType = 1;
        SemaphoreP_post(RxgSyncSem);
    }
    if(isrType == 2)
    {
        UART_printf("ERROR ISR, Interrupt Status: 0x%x\n", gMcanIsrIntr1Status);
    }
}

int32_t appRemoteServiceMcan2Init()
{
    int32_t status = 0;

    status = appRemoteServiceRegister(
        APP_REMOTE_SERVICE_MCAN2_NAME, appRemoteServiceMCAN2Handler);
    if(status!=0)
    {
        UART_printf(
            " REMOTE_SERVICE_MCAN2: ERROR: Unable to register remote service MCAN2 handler\n");
    }
    else
    {
        UART_printf(
                    " REMOTE_SERVICE_MCAN2: Able to register remote service MCAN2 handler\n");
    }
    return status;
}

int32_t appRemoteServiceMcan2DeInit()
{
    int32_t status = 0;

    status = appRemoteServiceUnRegister(APP_REMOTE_SERVICE_MCAN2_NAME);
    if(status!=0)
    {
        UART_printf(
            " REMOTE_SERVICE_MCAN2: ERROR: Unable to register remote service MCAN2 handler\n");
    }

    return status;
}

int32_t appRemoteServiceMCAN2Handler(char *service_name, uint32_t cmd,
    void *prm, uint32_t prm_size, uint32_t flags)
{
    int32_t  status = CSL_PASS;
    int i;
    if(prm!=NULL && prm_size == sizeof(uint32_t))
     {
         uintptr_t addr = (uintptr_t)(*(volatile uint32_t*)prm);
         //uint32_t value = *(volatile uint32_t*)addr;

         uint32_t *cmd_prms = (volatile uint32_t*)addr;
         appMemCacheInv((void*)addr, 256);
         for(i = 0;i< 10;i++)
         {
             printf("MCU2_1 : %d,\t",cmd_prms[i]);
         }
         printf("\n");
     }
   return status;
}



#if defined(R5F) && defined(SYSBIOS)
int32_t appMCAN2DeInit()
{
    /* MCAN2_deInit(); */

   return 0;
}
#endif

#ifdef TIMER_CALL
#if (TX_CODE) || (TX_RX_CODE)
void Txtest()
{
   MCAN_ProtocolStatus protStatus;

   st_OP_Signal_1 pd_dcan_msg_final;
   st_OP_Signal_0 pd_dcan_msg;

   uint32_t obj = 0,loopCnt = 0,obj_count = 0;

   /* Enable Transmission interrupt */
   uint32_t status = MCAN_txBufTransIntrEnable(gMcanModAddr,
                                          1U,
                                          (uint32_t)TRUE);
   while(1)
   {
       for (obj = 0; obj < (NUM_OF_OBJECTS); obj++)
       {
           txMsg.id  = (uint32_t)((uint32_t)(mcan2TxMsgId[obj]) << 18U);

           for (loopCnt = 0; loopCnt < 8; loopCnt++)
           {
               pd_dcan_msg_final.pd_msg[loopCnt] = 0;
           }
            //Copy all signals
            pd_dcan_msg.dist_x = 122;
            pd_dcan_msg.dist_y = 123;
            pd_dcan_msg.vel_y = 134;
            pd_dcan_msg.vel_x = 122;

            pd_dcan_msg.obj_type = 5;//cmdPrms[obj].object_type;

            //Convert all signals to be signed
            pd_dcan_msg_final.st_PD_Fields.obj_type = pd_dcan_msg.obj_type;
            pd_dcan_msg_final.st_PD_Fields.roll_count = pd_dcan_msg.roll_count;

            pd_dcan_msg_final.st_PD_Fields.dist_x = (pd_dcan_msg.dist_x + 8192);
            pd_dcan_msg_final.st_PD_Fields.vel_x = (pd_dcan_msg.vel_x + 4096);
            pd_dcan_msg_final.st_PD_Fields.dist_y = (pd_dcan_msg.dist_y + 8192);
            pd_dcan_msg_final.st_PD_Fields.vel_y = (pd_dcan_msg.vel_y + 4096);

            for (loopCnt = 0; loopCnt < 8; loopCnt++)
            {
                txMsg.data[loopCnt] = pd_dcan_msg_final.pd_msg[loopCnt];
            }


           if (CSL_PASS != status)
           {
               UART_printf("\nError in enabling buffer Transmit interrupt...\n");
           }
           else
           {
               txMsg.dlc = 8;
               /* Write message to Msg RAM */
               MCAN_writeMsgRam(gMcanModAddr,
                                MCAN_MEM_TYPE_BUF,
                                1U,
                                &txMsg);
               /* Add request for transmission */
               status = MCAN_txBufAddReq(gMcanModAddr, 1U);
               if (CSL_PASS != status)
               {
                   UART_printf("\nError in Adding Transmission Request...\n");
                   break;
               }
               //UART_printf("in semaphore pend\n");
               SemaphoreP_pend(TxgSyncSem, SemaphoreP_WAIT_FOREVER);
               //UART_printf("out semaphore pend\n");
               MCAN_getProtocolStatus(gMcanModAddr, &protStatus);

               /* Checking for Errors */
               if (((MCAN_ERR_CODE_NO_ERROR == protStatus.lastErrCode) ||
                    (MCAN_ERR_CODE_NO_CHANGE == protStatus.lastErrCode)) &&
                   ((MCAN_ERR_CODE_NO_ERROR == protStatus.dlec) ||
                    (MCAN_ERR_CODE_NO_CHANGE == protStatus.dlec)) &&
                   (0U == protStatus.pxe))
               {
                //UART_printf("\nMessage successfully transferred with payload Bytes \n");
               }
               else
               {
                   UART_printf("\nError in transmission with payload Bytes:%d\n");
                   status = CSL_EFAIL;
                   break;
               }
           }
       }
       Task_sleep(33);
   }//while
}

#if defined(R5F) && defined(SYSBIOS)
static Void TxMain(UArg arg0, UArg arg1)
{
    UART_printf("Tx thread\n");
    Txtest();
}
static Void RxMain(UArg arg0, UArg arg1)
{
    UART_printf("Rx thread\n");
    Rxtest();
}
void Tx_Timer_task()
{

    UART_printf("TASK SLEEP APPROACH \n");
    uint32_t timePeriodInMilliSec = 33;  //3 sec
    SemaphoreP_Params semParams;

    SemaphoreP_Params_init(&semParams);
    semParams.mode = SemaphoreP_Mode_COUNTING;
    TxgSyncSem = SemaphoreP_create(0U, &semParams);

    Task_Params tskParams1;
   Task_Params_init(&tskParams1);

   tskParams1.arg0 = (UArg) NULL;
   tskParams1.arg1 = (UArg) NULL;
   tskParams1.priority = 8u;
   tskParams1.stack = gTskTxStackMain;
   tskParams1.stackSize = sizeof (gTskTxStackMain);
   Task_create(TxMain, &tskParams1, NULL);

   Task_Params tskParams2;
   Task_Params_init(&tskParams2);

   tskParams2.arg0 = (UArg) NULL;
   tskParams2.arg1 = (UArg) NULL;
   tskParams2.priority = 8u;
   tskParams2.stack = gTskRxStackMain;
   tskParams2.stackSize = sizeof (gTskRxStackMain);
   Task_create(RxMain, &tskParams2, NULL);
}
#endif
#endif

#if (RX_CODE) || (TX_RX_CODE)
#if defined(R5F) && defined(SYSBIOS)
void Rxtest()
{
    int32_t              testStatus = CSL_PASS;
    MCAN_ErrCntStatus    errCounter;
    MCAN_ProtocolStatus protStatus;
    MCAN_RxFIFOStatus fifoStatus;
    while(1)
    {
        SemaphoreP_pend(RxgSyncSem, SemaphoreP_WAIT_FOREVER);

        if(((gMcanIsrIntr1Status & MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ==
                                    MCAN_INTR_SRC_RX_FIFO0_NEW_MSG))
        {
            fifoStatus.num = (uint32_t)MCAN_RX_FIFO_NUM_0;
        }
        else
        {
            fifoStatus.num = (uint32_t)MCAN_RX_FIFO_NUM_1;
        }

        MCAN_getRxFIFOStatus(APP_MCAN2_BASEADDR, &fifoStatus);
        MCAN_readMsgRam(APP_MCAN2_BASEADDR,
                        MCAN_MEM_TYPE_FIFO,
                        fifoStatus.getIdx,
                        (uint32_t)fifoStatus.num,
                        &rxMsg);
        (void) MCAN_writeRxFIFOAck(APP_MCAN2_BASEADDR,
                                   (uint32_t)fifoStatus.num,
                                   fifoStatus.getIdx);

        MCAN_getProtocolStatus(APP_MCAN2_BASEADDR, &protStatus);

       /* Checking for Errors */
       if (((MCAN_ERR_CODE_NO_ERROR == protStatus.lastErrCode) ||
            (MCAN_ERR_CODE_NO_CHANGE == protStatus.lastErrCode)) &&
           ((MCAN_ERR_CODE_NO_ERROR == protStatus.dlec) ||
            (MCAN_ERR_CODE_NO_CHANGE == protStatus.dlec)) &&
           (0U == protStatus.pxe))
       {
    //       UART_printf("\n(%dth) Message successfully received.%d , %d, %d ,%d \n",
    //                   rxMsg.id,rxMsg.data[0],rxMsg.data[1],rxMsg.data[2],rxMsg.data[3]);
       }
       else
       {
           UART_printf("\nError in reception message.\n");
       }
    }//while
}
void Rx_Timer_task()
{
    int32_t status = CSL_PASS;

    Board_pinmuxUpdate(gCockpitDemoPinmuxDataInfo,
                       BOARD_SOC_DOMAIN_MAIN);

    /* Set drive strength */
    CSL_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE +
            CSL_WKUP_CTRL_MMR_CFG0_H_IO_DRVSTRNGTH0_PROXY, 0xFU);

    CSL_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE +
            CSL_WKUP_CTRL_MMR_CFG0_V_IO_DRVSTRNGTH0_PROXY, 0xFU);

    SET_DEVICE_STATE(TISCI_DEV_MCAN2,
            TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
            status);

    SemaphoreP_Params semParams;

    SemaphoreP_Params_init(&semParams);
    semParams.mode = SemaphoreP_Mode_COUNTING;
    RxgSyncSem = SemaphoreP_create(0U, &semParams);
}
#endif

#endif
#endif

Thanks and Regards

Pooja Krishna

0 Karan Saxena over 4 years ago in reply to Pooja R1

TI__Guru* 75663 points

Hi Pooja,

Can you specify which prints are you talking about? And also in case when you remove prints and see that the application doesn't run - that means the Tx and Rx both stop, or one of them stops? And in all cases what is the interrupt status?

Regards,

Karan

0 Pooja R1 over 4 years ago in reply to Karan Saxena

Intellectual 790 points

Hi Karan,

1.THe following highlighted prints in Txtest() and Rxtest()

2. Also upon removing prints behavior is unstable ,sometimes Tx hangs and at other runs it doesnt even trigger mcan application.So I would like to know if introducing delay by adding print statements is allowing application to run properly.

Kindly suggest

Thanks and Regards

Pooja Krishna

0 Karan Saxena over 4 years ago in reply to Pooja R1

TI__Guru* 75663 points

Hi Pooja,

What is the interrupt status in cases when it hangs? That needs to be known so that we can root cause this.

I remember you had added that code in the ISR, can you post that log after you remove the prints?
Also, what data rate are you operating in? I see a macro but don't know if it is defined in some header file.

Regards,

Karan

0 Pooja R1 over 4 years ago in reply to Karan Saxena

Intellectual 790 points

Hi Karan,

1. Attaching the log file where all prints are off except interrupt status.Observed Tx to work for couple of time even reaching root login , as per log no prints came related to interrupt status.mcan_log_17apr.txt

2. Baud rate - 500 kbps

Thanks and Regards

Pooja Krishna

0 Pooja R1 over 4 years ago in reply to Pooja R1

Intellectual 790 points

Hello Karan,

As discussed following experiments and its observations are as below:-

1. Stress testing of standalone MCAN Tx+Rx with Auto re-transmission for Tx messages enabled and without invoking camera based app ran properly for 30 mins.

2. Experimented with priority of mcu2_1 main() set as 8u and MCAN task as 15u. It did not allow to boot the board, attached log as below:-

Priority.txt




















































U-Boot SPL 2019.01-g66126341c8 (Oct 24 2019 - 03:52:25 +0000)
SYSFW ABI: 2.6 (firmware rev 0x0013 '19.8.0-v2019.08 (Terrific Llama')
Trying to boot from MMC2
Loading Environment from MMC... *** Warning - No MMC card found, using default environment

Remoteproc 2 started successfully
** File not found /lib/firmware/j7-mcu-r5f0_0-fw **
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.1(release):ti2019.02-rc4
NOTICE:  BL31: Built : 03:52:00, Oct 24 2019
I/TC: 
I/TC: OP-TEE version: ti2019.02-89-ge5a8779-dev (gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))) #1 Thu Oct 24 03:52:22 UTC 2019 aarch64
I/TC: Initialized

U-Boot SPL 2019.01-g66126341c8 (Oct 24 2019 - 03:52:45 +0000)
Detected: J7X-BASE-CPB rev E2
Detected: J7X-VSC8514-ETH rev E2
Trying to boot from MMC2


U-Boot 2019.01-g66126341c8 (Oct 24 2019 - 03:52:45 +0000)

SoC:   J721E PG 1.0
Model: Texas Instruments K3 J721E SoC
Board: J721EX-PM1-SOM rev E2
DRAM:  4 GiB
Flash: 0 Bytes
MMC:   sdhci@4f80000: 0, sdhci@4fb0000: 1
Loading Environment from MMC... *** Warning - bad CRC, using default environment

In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
Detected: J7X-BASE-CPB rev E2
Detected: J7X-VSC8514-ETH rev E2
Net:   
Warning: ethernet@046000000 using MAC address from ROM
eth0: ethernet@046000000
Hit any key to stop autoboot:  0 
switch to partitions #0, OK
mmc1 is current device
SD/MMC found on device 1
** Unable to read file boot.scr **
81 bytes read in 0 ms
Loaded env from uEnv.txt
Importing environment from mmc1 ...
12713136 bytes read in 531 ms (22.8 MiB/s)
Load Remote Processor 3 with data@addr=0x80080000 12713136 bytes: Success!
** File not found /lib/firmware/j7-main-r5f1_0-fw **
CrossBar/Interrupt Configuration done.
MCANSS Revision ID:
scheme:0x1
Business Unit:0x2
Module ID:0x8e0
RTL Revision:0x9
Major Revision:0x1
Custom Revision:0x0
Minor Revision:0x1
CAN-FD operation is enabled through E-Fuse.
Endianess Value: 0x87654321
18710400 bytes read in 2978 ms (6 MiB/s)
Load Remote Processor 6 with data@addr=0x80080000 18710400 bytes: Success!
18643928 bytes read in 775 ms (22.9 MiB/s)
Load Remote Processor 7 with data@addr=0x80080000 18643928 bytes: Success!
11860696 bytes read in 1784 ms (6.3 MiB/s)
Load Remote Processor 8 with data@addr=0x80080000 11860696 bytes: Success!
13338632 bytes read in 559 ms (22.8 MiB/s)
100093 bytes read in 5 ms (19.1 MiB/s)
3653 bytes read in 2 ms (1.7 MiB/s)
3742 bytes read in 3 ms (1.2 MiB/s)
## Flattened Device Tree blob at 82000000
   Booting using the fdt blob at 0x82000000
   Loading Device Tree to 00000000fdda5000, end 00000000fdec0fff ... OK

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080]
[    0.000000] Linux version 4.19.73-g0cabba2b47 (oe-user@oe-host) (gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))) #1 SMP PREEMPT Thu Oct 24 03:54:33 UTC 2019
[    0.000000] Machine model: Texas Instruments K3 J721E SoC
[    0.000000] earlycon: ns16550a0 at MMIO32 0x0000000002800000 (options '')
[    0.000000] bootconsole [ns16550a0] enabled
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a0000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a0000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a0100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a0100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a1000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a1000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a1100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a1100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a2000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a2000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a2100000, size 31 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a2100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a4000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a3000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a4100000, size 63 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a3100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a8000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a4000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a8100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a4100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a9000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a5000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a9100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a5100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000aa000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node c66-dma-memory@a6000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000aa100000, size 63 MiB
[    0.000000] OF: reserved mem: initialized node c66-memory@a6100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000ae000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node c66-dma-memory@a7000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000ae100000, size 31 MiB
[    0.000000] OF: reserved mem: initialized node c66-memory@a7100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000b0000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node c71-dma-memory@a8000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000b0100000, size 127 MiB
[    0.000000] OF: reserved mem: initialized node c71-memory@a8100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000b8000000, size 32 MiB
[    0.000000] OF: reserved mem: initialized node vision_apps-dma-memory@b8000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000bc000000, size 576 MiB
[    0.000000] OF: reserved mem: initialized node vision_apps_shared-memories@bc000000, compatible id shared-dma-pool
[    0.000000] cma: Failed to reserve 512 MiB
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: Trusted OS migration not required
[    0.000000] psci: SMC Calling Convention v1.1
[    0.000000] random: get_random_bytes called from start_kernel+0x94/0x3e4 with crng_init=0
[    0.000000] percpu: Embedded 2 pages/cpu s52632 r8192 d70248 u131072
[    0.000000] Detected PIPT I-cache on CPU0
[    0.000000] CPU features: enabling workaround for EL2 vector hardening
[    0.000000] Speculative Store Bypass Disable mitigation not required
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 57927
[    0.000000] Kernel command line: console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000 mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backut
[    0.000000] Dentry cache hash table entries: 524288 (order: 6, 4194304 bytes)
[    0.000000] Inode-cache hash table entries: 262144 (order: 5, 2097152 bytes)
[    0.000000] software IO TLB: mapped [mem 0xf9da0000-0xfdda0000] (64MB)
[    0.000000] Memory: 3029504K/3710976K available (8510K kernel code, 738K rwdata, 3136K rodata, 576K init, 642K bss, 681472K reserved, 0K cma-reserved)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[    0.000000] rcu: Preemptible hierarchical RCU implementation.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=2.
[    0.000000]  Tasks RCU enabled.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode
[    0.000000] GICv3: Distributor has no Range Selector support
[    0.000000] GICv3: no VLPI support, no direct LPI support
[    0.000000] ITS [mem 0x01820000-0x0182ffff]
[    0.000000] GIC: enabling workaround for ITS: Socionext Synquacer pre-ITS
[    0.000000] ITS@0x0000000001820000: allocated 1048576 Devices @8c0800000 (flat, esz 8, psz 64K, shr 0)
[    0.000000] ITS: using cache flushing for cmd queue
[    0.000000] GIC: using LPI property table @0x00000008c00a0000
[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000001900000
[    0.000000] CPU0: using LPI pending table @0x00000008c00b0000
[    0.000000] GIC: using cache flushing for LPI property table
[    0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2e2049d3e8, max_idle_ns: 440795210634 ns
[    0.000002] sched_clock: 56 bits at 200MHz, resolution 5ns, wraps every 4398046511102ns
[    0.008371] Console: colour dummy device 80x25
[    0.012931] Calibrating delay loop (skipped), value calculated using timer frequency.. 400.00 BogoMIPS (lpj=800000)
[    0.023601] pid_max: default: 32768 minimum: 301
[    0.028343] Security Framework initialized
[    0.032548] Mount-cache hash table entries: 8192 (order: 0, 65536 bytes)
[    0.039405] Mountpoint-cache hash table entries: 8192 (order: 0, 65536 bytes)
[    0.070752] ASID allocator initialised with 32768 entries
[    0.084280] rcu: Hierarchical SRCU implementation.
[    0.097243] Platform MSI: gic-its@1820000 domain created
[    0.102877] PCI/MSI: /interconnect@100000/interrupt-controller@1800000/gic-its@1820000 domain created
[    0.120313] smp: Bringing up secondary CPUs ...
[    0.157234] Detected PIPT I-cache on CPU1
[    0.157257] GICv3: CPU1: found redistributor 1 region 0:0x0000000001920000
[    0.157288] CPU1: using LPI pending table @0x00000008c0310000
[    0.157318] CPU1: Booted secondary processor 0x0000000001 [0x411fd080]
[    0.157373] smp: Brought up 1 node, 2 CPUs
[    0.185213] SMP: Total of 2 processors activated.
[    0.190024] CPU features: detected: GIC system register CPU interface
[    0.196605] CPU features: detected: 32-bit EL0 Support
[    0.202112] CPU: All CPU(s) started at EL2
[    0.206300] alternatives: patching kernel code
[    0.211401] devtmpfs: initialized
[    0.219913] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.229882] futex hash table entries: 512 (order: -1, 32768 bytes)
[    0.236319] pinctrl core: initialized pinctrl subsystem
[    0.242051] NET: Registered protocol family 16
[    0.246952] vdso: 2 pages (1 code @ (____ptrval____), 1 data @ (____ptrval____))
[    0.254516] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.261613] DMA: preallocated 256 KiB pool for atomic allocations
[    0.275016] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[    0.281874] HugeTLB registered 512 MiB page size, pre-allocated 0 pages
[    0.289343] cryptd: max_cpu_qlen set to 1000
[    0.294333] vsys_3v3: supplied by evm_12v0
[    0.298603] vsys_5v0: supplied by evm_12v0
[    0.303139] SCSI subsystem initialized
[    0.307197] media: Linux media interface: v0.10
[    0.311832] videodev: Linux video capture interface: v2.00
[    0.317446] pps_core: LinuxPPS API ver. 1 registered
[    0.322515] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.331852] PTP clock support registered
[    0.335862] EDAC MC: Ver: 3.0.0
[    0.339734] Advanced Linux Sound Architecture Driver Initialized.
[    0.346354] clocksource: Switched to clocksource arch_sys_counter
[    0.352662] VFS: Disk quotas dquot_6.6.0
[    0.356707] VFS: Dquot-cache hash table entries: 8192 (order 0, 65536 bytes)
[    0.366313] NET: Registered protocol family 2
[    0.371088] tcp_listen_portaddr_hash hash table entries: 4096 (order: 0, 65536 bytes)
[    0.379141] TCP established hash table entries: 32768 (order: 2, 262144 bytes)
[    0.386625] TCP bind hash table entries: 32768 (order: 3, 524288 bytes)
[    0.393882] TCP: Hash tables configured (established 32768 bind 32768)
[    0.400615] UDP hash table entries: 2048 (order: 0, 65536 bytes)
[    0.406802] UDP-Lite hash table entries: 2048 (order: 0, 65536 bytes)
[    0.413491] NET: Registered protocol family 1
[    0.418183] RPC: Registered named UNIX socket transport module.
[    0.424238] RPC: Registered udp transport module.
[    0.429041] RPC: Registered tcp transport module.
[    0.433844] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.440738] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
[    0.450416] Initialise system trusted keyrings
[    0.455026] workingset: timestamp_bits=46 max_order=16 bucket_order=0
[    0.463168] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.469358] NFS: Registering the id_resolver key type
[    0.474527] Key type id_resolver registered
[    0.478800] Key type id_legacy registered
[    0.482898] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[    0.489823] 9p: Installing v9fs 9p2000 file system support
[    0.496929] Key type asymmetric registered
[    0.501117] Asymmetric key parser 'x509' registered
[    0.506124] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
[    0.513684] io scheduler noop registered
[    0.517690] io scheduler deadline registered
[    0.522097] io scheduler cfq registered (default)
[    0.526904] io scheduler mq-deadline registered
[    0.531530] io scheduler kyber registered
[    0.536458] pinctrl-single 4301c000.pinmux: 94 pins, size 376
[    0.542554] pinctrl-single 11c000.pinmux: 173 pins, size 692
[    0.548701] pinctrl-single a40000.timesync_router: 512 pins, size 2048
[    0.557810] ti-pat 31010000.pat: Found PAT Rev 1.0 with 16384 pages
[    0.564243] ti-pat 31010000.pat: Failed to create 31010000.pat debugfs directory
[    0.571941] ti-pat 31011000.pat: Found PAT Rev 1.0 with 16384 pages
[    0.578369] ti-pat 31011000.pat: Failed to create 31011000.pat debugfs directory
[    0.586011] ti-pat 31012000.pat: Found PAT Rev 1.0 with 16384 pages
[    0.592425] ti-pat 31012000.pat: Failed to create 31012000.pat debugfs directory
[    0.600060] ti-pat 31013000.pat: Found PAT Rev 1.0 with 2048 pages
[    0.606382] ti-pat 31013000.pat: Failed to create 31013000.pat debugfs directory
[    0.614012] ti-pat 31014000.pat: Found PAT Rev 1.0 with 2048 pages
[    0.620335] ti-pat 31014000.pat: Failed to create 31014000.pat debugfs directory
[    0.629306] Serial: 8250/16550 driver, 10 ports, IRQ sharing enabled
[    0.637156] panel-simple dummy-panel: dummy-panel supply power not found, using dummy regulator
[    0.646090] panel-simple dummy-panel: Linked as a consumer to regulator.0
[    0.656645] brd: module loaded
[    0.662647] loop: module loaded
[    0.667086] libphy: Fixed MDIO Bus: probed
[    0.671421] tun: Universal TUN/TAP device driver, 1.6
[    0.676833] igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.4.0-k
[    0.684839] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
[    0.690904] sky2: driver version 1.30
[    0.695230] VFIO - User Level meta-driver version: 0.3
[    0.700867] i2c /dev entries driver
[    0.704874] sdhci: Secure Digital Host Controller Interface driver
[    0.711188] sdhci: Copyright(c) Pierre Ossman
[    0.715830] sdhci-pltfm: SDHCI platform and OF driver helper
[    0.722054] ledtrig-cpu: registered to indicate activity on CPUs
[    0.795958] optee: probing for conduit method from DT.
[    0.801227] optee: revision 3.6 (e5a8779a)
[    0.801347] optee: initialized driver
[    0.810022] NET: Registered protocol family 17
[    0.814639] 9pnet: Installing 9P2000 support
[    0.819028] Key type dns_resolver registered
[    0.823661] registered taskstats version 1
[    0.827846] Loading compiled-in X.509 certificates
[    0.836890] ti-sci 44083000.dmsc: ABI: 2.6 (firmware rev 0x0013 '19.8.0-v2019.08 (Terrific Llama')
[    0.862511] random: fast init done
[    0.903908] omap_i2c 40b00000.i2c: bus 0 rev0.12 at 100 kHz
[    0.909879] omap_i2c 40b10000.i2c: bus 1 rev0.12 at 100 kHz
[    0.916070] palmas 2-0058: IRQ missing: skipping irq request
[    0.942611] palmas 2-0058: Muxing GPIO 5d, PWM 0, LED 0
[    0.948533] SMPS3: supplied by regulator-dummy
[    0.953782] SMPS4: supplied by regulator-dummy
[    0.959033] SMPS5: supplied by regulator-dummy
[    0.964261] SMPS12: supplied by regulator-dummy
[    0.969539] LDO1: supplied by vsys_3v3
[    0.973764] ldo1: Bringing 900000uV into 1800000-1800000uV
[    0.981620] LDO2: supplied by regulator-dummy
[    0.986466] ldo2: Bringing 900000uV into 3300000-3300000uV
[    0.995150] LDO3: supplied by regulator-dummy
[    1.000033] LDO4: supplied by regulator-dummy
[    1.004914] LDO5: supplied by regulator-dummy
[    1.009906] omap_i2c 42120000.i2c: bus 2 rev0.12 at 400 kHz
[    1.016004] pca953x 3-0020: 3-0020 supply vcc not found, using dummy regulator
[    1.023410] pca953x 3-0020: Linked as a consumer to regulator.0
[    2.066356] omap_i2c 2000000.i2c: controller timed out
[    2.071609] pca953x 3-0020: failed reading register
[    2.076616] pca953x 3-0020: Dropping the link to regulator.0
[    2.082413] pca953x: probe of 3-0020 failed with error -110
[    2.088196] pca953x 3-0022: 3-0022 supply vcc not found, using dummy regulator
[    2.095600] pca953x 3-0022: Linked as a consumer to regulator.0
[    3.154357] omap_i2c 2000000.i2c: controller timed out
[    3.159611] pca953x 3-0022: failed reading register
[    3.164606] pca953x 3-0022: Dropping the link to regulator.0
[    3.170395] pca953x: probe of 3-0022 failed with error -110
[    3.176113] omap_i2c 2000000.i2c: bus 3 rev0.12 at 400 kHz
[    3.182020] omap_i2c 2020000.i2c: bus 4 rev0.12 at 100 kHz
[    3.187951] pca953x 5-0020: 5-0020 supply vcc not found, using dummy regulator
[    3.195353] pca953x 5-0020: Linked as a consumer to regulator.0
[    3.223021] GPIO line 504 (CODEC_RSTz) hogged as output/high
[    3.228921] omap_i2c 2030000.i2c: bus 5 rev0.12 at 400 kHz
[    3.234792] omap_i2c 2040000.i2c: bus 6 rev0.12 at 100 kHz
[    3.240644] omap_i2c 2050000.i2c: bus 7 rev0.12 at 100 kHz
[    3.255235] cdns-pcie-host d000000.pcie: missing "mem"
[    3.260797] cdns-pcie-host d800000.pcie: missing "mem"
[    3.266315] cdns-pcie-host e000000.pcie: missing "mem"
[    3.271967] k3-ringacc 2b800000.ringacc: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:235
[    3.281847] k3-ringacc 2b800000.ringacc: dma-ring-reset-quirk: disabled
[    3.288608] k3-ringacc 2b800000.ringacc: RA Proxy rev. 66346100, num_proxies:64
[    3.296296] k3-ringacc 3c000000.ringacc: Ring Accelerator probed rings:1024, gp-rings[440,150] sci-dev-id:211
[    3.306435] k3-ringacc 3c000000.ringacc: dma-ring-reset-quirk: disabled
[    3.313194] k3-ringacc 3c000000.ringacc: RA Proxy rev. 66346100, num_proxies:64
[    3.320812] omap8250 40a00000.serial: PM domain pd:149 will not be powered off
[    3.328363] 40a00000.serial: ttyS1 at MMIO 0x40a00000 (irq = 7, base_baud = 6000000) is a 8250
[    3.337491] 2800000.serial: ttyS2 at MMIO 0x2800000 (irq = 18, base_baud = 3000000) is a 8250
[    3.346233] console [ttyS2] enabled
[    3.346233] console [ttyS2] enabled
[    3.353268] bootconsole [ns16550a0] disabled
[    3.353268] bootconsole [ns16550a0] disabled
[    3.362184] 2810000.serial: ttyS3 at MMIO 0x2810000 (irq = 19, base_baud = 3000000) is a 8250
[    3.370993] 2840000.serial: ttyS6 at MMIO 0x2840000 (irq = 20, base_baud = 3000000) is a 8250
[    3.379716] arm-smmu-v3 36600000.smmu: ias 48-bit, oas 48-bit (features 0x00001faf)
[    3.388439] arm-smmu-v3 36600000.smmu: msi_domain absent - falling back to wired irqs
[    3.397244] tidss 4a00000.dss: dispc7_wb_find_free_ovr: No OVR available for WB, disabling WB.
[    3.405845] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[    3.412443] [drm] No driver support for vblank timestamp query.
[    3.419777] [drm] Initialized tidss 1.0.0 20180215 for 4a00000.dss on minor 0
[    3.481058] Console: switching to colour frame buffer device 240x67
[    3.503636] tidss 4a00000.dss: fb0: DRM emulated frame buffer device
[    3.514533] cdns-ufshcd 4e84000.ufs: ufshcd_populate_vreg: Unable to find vdd-hba-supply regulator, assuming enabled
[    3.525036] cdns-ufshcd 4e84000.ufs: ufshcd_populate_vreg: Unable to find vcc-supply regulator, assuming enabled
[    3.535195] cdns-ufshcd 4e84000.ufs: ufshcd_populate_vreg: Unable to find vccq-supply regulator, assuming enabled
[    3.545438] cdns-ufshcd 4e84000.ufs: ufshcd_populate_vreg: Unable to find vccq2-supply regulator, assuming enabled
[    3.556220] scsi host0: ufshcd
[    3.572940] cadence-qspi 47040000.spi: mt35xu512aba (65536 Kbytes)
[    3.579129] 7 cmdlinepart partitions found on MTD device 47040000.spi.0
[    3.585728] Creating 7 MTD partitions on "47040000.spi.0":
[    3.591210] 0x000000000000-0x000000080000 : "ospi.tiboot3"
[    3.591213] cdns-ufshcd 4e84000.ufs: ufshcd_print_pwr_info:[RX, TX]: gear=[1, 1], lane[1, 1], pwr[SLOWAUTO_MODE, SLOWAUTO_MODE], rate = 0
[    3.609349] 0x000000080000-0x000000280000 : "ospi.tispl"
[    3.614854] 0x000000280000-0x000000680000 : "ospi.u-boot"
[    3.620431] 0x000000680000-0x0000006a0000 : "ospi.env"
[    3.625810] 0x0000006a0000-0x0000006c0000 : "ospi.env.backup"
[    3.631819] 0x0000006c0000-0x0000007c0000 : "ospi.sysfw"
[    3.637317] 0x000000800000-0x000004000000 : "ospi.rootfs"
[    3.655626] cdns-ufshcd 4e84000.ufs: ufshcd_print_pwr_info:[RX, TX]: gear=[3, 3], lane[2, 2], pwr[FAST MODE, FAST MODE], rate = 2
[    3.667313] cdns-ufshcd 4e84000.ufs: ufshcd_find_max_sup_active_icc_level: Regulator capability was not set, actvIccLevel=0
[    3.678579] scsi 0:0:0:49488: Well-known LUN    TOSHIBA  THGAF8G8T23BAILB 0300 PQ: 0 ANSI: 6
[    3.687317] scsi 0:0:0:49476: Well-known LUN    TOSHIBA  THGAF8G8T23BAILB 0300 PQ: 0 ANSI: 6
[    3.696072] cdns-ufshcd 4e84000.ufs: ufshcd_scsi_add_wlus: BOOT WLUN not found
[    3.786443] cadence-qspi 47040000.spi: Cadence QSPI NOR probe failed -517
[    3.794063] cadence-qspi 47050000.spi: n25q512a (65536 Kbytes)
[    3.814441] cadence-qspi 47050000.spi: Cadence QSPI NOR probe failed -517
[    3.821767] am65-cpsw-nuss 46000000.ethernet: rx-flow-id-base is not set -22
[    3.828832] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA00101, cpsw version 0x6BA80100 Ports: 2
[    3.840244] UDMA has not been proped
[    3.843819] am65-cpsw-nuss 46000000.ethernet: Failed to request tx dma channel -517
[    3.852310] am65-cpts 310d0000.cpts: CPTS ver 0x4e8a010a, freq:200000000, add_val:4 pps:0
[    3.860863] mmc0: Unknown controller version (4). You may experience problems.
[    3.868095] mmc0: CQHCI version 5.10
[    3.902399] mmc0: SDHCI controller on 4f80000.sdhci [4f80000.sdhci] using ADMA 64-bit
[    3.910595] sdhci-am654 4fb0000.sdhci: Linked as a consumer to regulator.8
[    3.917640] sdhci-am654 4fb0000.sdhci: Dropping the link to regulator.8
[    3.930511] omap-mailbox 31f80000.mailbox: omap mailbox rev 0x66fc7100
[    3.937476] omap-mailbox 31f81000.mailbox: omap mailbox rev 0x66fc7100
[    3.944510] omap-mailbox 31f82000.mailbox: omap mailbox rev 0x66fc7100
[    3.951397] omap-mailbox 31f83000.mailbox: omap mailbox rev 0x66fc7100
[    3.958303] omap-mailbox 31f84000.mailbox: omap mailbox rev 0x66fc7100
[    3.988385] mmc0: Command Queue Engine enabled
[    3.992833] mmc0: new HS400 MMC card at address 0001
[    3.998241] mmcblk0: mmc0:0001 S0J56X 14.8 GiB 
[    4.003076] mmcblk0boot0: mmc0:0001 S0J56X partition 1 31.5 MiB
[    4.009317] mmcblk0boot1: mmc0:0001 S0J56X partition 2 31.5 MiB
[    4.015337] mmcblk0rpmb: mmc0:0001 S0J56X partition 3 4.00 MiB, chardev (242:0)
[    4.275559] cdns-pcie-host d000000.pcie: missing "mem"
[    4.280892] cdns-pcie-host d800000.pcie: missing "mem"
[    4.286135] cdns-pcie-host e000000.pcie: missing "mem"
[    4.291980] ti-udma 285c0000.udmap: Channels: 24 (tchan: 48, echan: 0, rchan: 48, rflow: 96)
[    4.301573] ti-udma 31150000.udmap: Channels: 84 (tchan: 140, echan: 160, rchan: 140, rflow: 300)
[    4.313840] cadence-qspi 47040000.spi: mt35xu512aba (65536 Kbytes)
[    4.320025] 7 cmdlinepart partitions found on MTD device 47040000.spi.0
[    4.326631] Creating 7 MTD partitions on "47040000.spi.0":
[    4.332106] 0x000000000000-0x000000080000 : "ospi.tiboot3"
[    4.337943] 0x000000080000-0x000000280000 : "ospi.tispl"
[    4.343449] 0x000000280000-0x000000680000 : "ospi.u-boot"
[    4.349029] 0x000000680000-0x0000006a0000 : "ospi.env"
[    4.354405] 0x0000006a0000-0x0000006c0000 : "ospi.env.backup"
[    4.360349] 0x0000006c0000-0x0000007c0000 : "ospi.sysfw"
[    4.365843] 0x000000800000-0x000004000000 : "ospi.rootfs"
[    4.373565] cadence-qspi 47050000.spi: n25q512a (65536 Kbytes)
[    4.381337] am65-cpsw-nuss 46000000.ethernet: rx-flow-id-base is not set -22
[    4.388400] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA00101, cpsw version 0x6BA80100 Ports: 2
[    4.405584] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48
[    4.416026] pps pps0: new PPS source ptp1
[    4.420121] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010a, freq:500000000, add_val:1 pps:1
[    4.429071] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 0.4
[    4.436277] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[    4.478358] am65-cpsw-nuss 46000000.ethernet: davinci mdio revision 9.7, bus freq 1000000
[    4.486519] libphy: 46000000.ethernet: probed
[    4.492238] sdhci-am654 4fb0000.sdhci: Linked as a consumer to regulator.8
[    4.499233] sdhci-am654 4fb0000.sdhci: Dropping the link to regulator.8
[    4.513026] cdns-pcie-host d000000.pcie: missing "mem"
[    4.518277] cdns-pcie-host d800000.pcie: missing "mem"
[    4.523519] cdns-pcie-host e000000.pcie: missing "mem"
[    4.529037] sdhci-am654 4fb0000.sdhci: Linked as a consumer to regulator.8
[    4.536023] sdhci-am654 4fb0000.sdhci: Dropping the link to regulator.8
[    4.542841] cdns-pcie-host d000000.pcie: missing "mem"
[    4.548071] cdns-pcie-host d800000.pcie: missing "mem"
[    4.553314] cdns-pcie-host e000000.pcie: missing "mem"
[    4.558793] sdhci-am654 4fb0000.sdhci: Linked as a consumer to regulator.8
[    4.565771] sdhci-am654 4fb0000.sdhci: Dropping the link to regulator.8
[    4.574018] input: gpio-keys as /devices/platform/gpio-keys/input/input0
[    4.581101] cdns-pcie-host d000000.pcie: missing "mem"
[    4.582422] hctosys: unable to open rtc device (rtc0)
[    4.586353] cdns-pcie-host d800000.pcie: missing "mem"
[    4.596552] cdns-pcie-host e000000.pcie: missing "mem"
[    4.621917] ldo1: disabling
[    4.624940] ALSA device list:
[    4.624957] sdhci-am654 4fb0000.sdhci: Linked as a consumer to regulator.8
[    4.627901]   No soundcards found.
[    4.638298] sdhci-am654 4fb0000.sdhci: Dropping the link to regulator.8
[    4.645036] Waiting for root device PARTUUID=c4f415dd-02...

3. Experiment done to confirm if hang is happening in either Tx or Rx or both after invoking camera based app.Observed that number of hits of Tx and Rx tally with total hits in ISR.

Observed that once camera application is triggered ,mcan hangs after running for certain number of frames.

4. Error status "0x80u" is not observed if I dont send messages from IG generator.Also by modifying below parameters, error status 80u stopped coming after application is invoked.

msgRAMConfigParams.rxFIFO1size = 10;//APP_MCAN_FIFO_1_NUM;

msgRAMConfigParams.txEventFIFOSize = 10u;//APP_MCAN_TX_BUFF_SIZE;

ERROR ISR, Interrupt Status: 0x0 keeps coming in console.

5. Also MCAN Tx + Rx with single object was running for 30mins even after invoking camera based application.Upon increasing the num of objects to 5 it again hanged after some time.

Thanks and Regards

Pooja Krishna

0 Karan Saxena over 4 years ago in reply to Pooja R1

TI__Guru* 75663 points

Hi Pooja,

1. Looks good, so standalone CAN works fine. (even with more number of objects)

2. Can you provide the source for this? main() you refer here is which main(), that too is a task?

3. The screenshot you attached, is that after the crash? I would have expected the num_Tx to be way more than the num_Rx (although adding to num_ISR) because the Tx is happening every 33ms but for a batch of NUM_OF_OBJECTS, while Rx happens once every 33ms.

4. Looks good, we should not get 0x80 after Rx_task starts if we are able to consume messages at a rate greater than we send from CAN emulator.

But I would say the 0x0 is still a mystery, we can do a couple of things here -

a. Make the gMcanIsrIntr1Status variable local to the ISR, this would ensure that no-one else is modifying it. I see you use this in the Rxtest(), you can either again get the MCAN_getIntrStatus(someLocalVarToRxtest); But do NOT clear it here.

b. Modify the UART_printf("ERROR ISR, Interrupt Status: 0x%x\n", gMcanIsrIntr1Status); to UART_printf("ERROR ISR, Interrupt Status: 0x%x!!\n", gMcanIsrIntr1Status); This would ensure we are not missing some part of the print. "!!" will ensure the print indeed has completed. This is because I see at some places we have some part of the print in one line and some in the other, due to shared UART.

5. This is an interesting data point, in this case do you get Error ISR prints?

Can you please share the logs for the above cases?

Regards,

Karan

0 Pooja R1 over 4 years ago in reply to Karan Saxena

Intellectual 790 points

Hello Karan,

#2 -> Path :- ../psdk_rtos_auto_j7_06_01_00_15/vision_apps/apps/basic_demos/app_tirtos/tirtos_linux/mcu2_1/main.c

5023.main.c

/*
 *
 * Copyright (c) 2018 Texas Instruments Incorporated
 *
 * All rights reserved not granted herein.
 *
 * Limited License.
 *
 * Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
 * license under copyrights and patents it now or hereafter owns or controls to make,
 * have made, use, import, offer to sell and sell ("Utilize") this software subject to the
 * terms herein.  With respect to the foregoing patent license, such license is granted
 * solely to the extent that any such patent is necessary to Utilize the software alone.
 * The patent license shall not apply to any combinations which include this software,
 * other than combinations with devices manufactured by or for TI ("TI Devices").
 * No hardware patent is licensed hereunder.
 *
 * Redistributions must preserve existing copyright notices and reproduce this license
 * (including the above copyright notice and the disclaimer and (if applicable) source
 * code license limitations below) in the documentation and/or other materials provided
 * with the distribution
 *
 * Redistribution and use in binary form, without modification, are permitted provided
 * that the following conditions are met:
 *
 * *       No reverse engineering, decompilation, or disassembly of this software is
 * permitted with respect to any software provided in binary form.
 *
 * *       any redistribution and use are licensed by TI for use only with TI Devices.
 *
 * *       Nothing shall obligate TI to provide you with source code for the software
 * licensed and provided to you in object code.
 *
 * If software source code is provided to you, modification and redistribution of the
 * source code are permitted provided that the following conditions are met:
 *
 * *       any redistribution and use of the source code, including any resulting derivative
 * works, are licensed by TI for use only with TI Devices.
 *
 * *       any redistribution and use of any object code compiled from the source code
 * and any resulting derivative works, are licensed by TI for use only with TI Devices.
 *
 * Neither the name of Texas Instruments Incorporated nor the names of its suppliers
 *
 * may be used to endorse or promote products derived from this software without
 * specific prior written permission.
 *
 * DISCLAIMER.
 *
 * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
 * OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

#include <app.h>
#include <utils/console_io/include/app_log.h>
#include <stdio.h>
#include <string.h>
#include <xdc/runtime/Error.h>
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Task.h>
#include <app_ipc_rsctable.h>
#include "utils/mcan/app_mcan2.h"

//static Void TxMain(UArg arg0, UArg arg1)
//{
//    while(1)
//    {
//        printf("Txmain\n");
//        Txtest();
//        Task_sleep(33);
//    }
//}
//
//static Void RxMain(UArg arg0, UArg arg1)
//{
//    while(1)
//    {
//        printf("RXmain\n");
//        Rxtest();
//        Task_sleep(33);
//    }
//
//}

static Void appMain(UArg arg0, UArg arg1)
{
    appInit();
    appRun();
    #if 1
    while(1)
    {
        appLogWaitMsecs(100u);
    }
    #else
    appDeInit();
    #endif
}

void StartupEmulatorWaitFxn (void)
{
    volatile uint32_t enableDebug = 0;
    do
    {
    }while (enableDebug);
}

static uint8_t gTskStackMain[8*1024]
__attribute__ ((section(".bss:taskStackSection")))
__attribute__ ((aligned(8192)))
    ;
static uint8_t gTskTxStackMain[8*1024]
__attribute__ ((section(".bss:taskStackSection")))
__attribute__ ((aligned(8192)))
    ;
volatile uint32_t debug_var = 1;
int main(void)
{
    Task_Params tskParams;
    Error_Block eb;
    Task_Handle task;

    /* This is for debug purpose - see the description of function header */
    //StartupEmulatorWaitFxn();
    while(debug_var);

    Error_init(&eb);
    Task_Params_init(&tskParams);

    tskParams.arg0 = (UArg) NULL;
    tskParams.arg1 = (UArg) NULL;
    tskParams.priority = 8u;
    tskParams.stack = gTskStackMain;
    tskParams.stackSize = sizeof (gTskStackMain);
    task = Task_create(appMain, &tskParams, &eb);

    //////////////////////////////////////////////////

    Task_Params tskParams1;
    Task_Params_init(&tskParams1);

    tskParams1.arg0 = (UArg) NULL;
    tskParams1.arg1 = (UArg) NULL;
    tskParams1.priority = 8u;
    tskParams1.stack = gTskTxStackMain;
    tskParams1.stackSize = sizeof (gTskTxStackMain);
    Task_create(appMcan2Init, &tskParams1, NULL);

    //////////////////////////////////////////////////

    if(NULL == task)
    {
        BIOS_exit(0);
    }
    BIOS_start();

    return 0;
}

uint32_t appGetDdrSharedHeapSize()
{
    return DDR_SHARED_MEM_SIZE;
}

#3 Attaching the screenshot after crash for 5 objects, made sure we cleared the counters before triggering camera application.So since 5 objects are transmitted if we divide num_Tx by 5 = 3970, which is lesser than Rx.So Rx is running for few more frames compared to Tx.

#4 In ISR, MCAN_getIntrStatus and MCAN_clearIntrStatus are called. So in Rxtest(),if I call MCAN_getIntrStatus() ->it would have been already cleared by ISR for "gMcanModAddr". So kindly clarify on this.

#5 Data Log of error status and also source code of app_mcan2.c is attached below:-

mcan_log_22apr.txt

4670.app_mcan2.c

/*
 *   Copyright (c) Texas Instruments Incorporated 2016-2019
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

/**
 *  \file     app_mcan2.c
 *
 *  \brief    This file contains MCAN sample code.
 *
 *  \details  MCAN operational mode is set to Classic CAN.
 *
 */

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
#define TIMER_CALL
#include <stdint.h>
#include <stdio.h>
#include <ti/csl/csl_types.h>
#include <ti/csl/soc.h>
#include <ti/csl/hw_types.h>
#include <ti/csl/arch/csl_arch.h>
#include <ti/csl/csl_mcan.h>
#include <ti/drv/uart/UART.h>
#include <ti/drv/uart/UART_stdio.h>
#include <ti/osal/osal.h>
#include <ti/drv/gpio/GPIO.h>
#include <ti/drv/gpio/soc/GPIO_soc.h>
#include <ti/csl/csl_gpio.h>
#include <ti/board/board.h>
#include <ti/drv/i2c/I2C.h>
#if defined (SOC_J721E)
#include <ti/drv/sciclient/sciclient.h>
#endif
#include <utils/mcan/app_mcan2.h>
#include <utils/remote_service/include/app_remote_service.h>
#include <utils/console_io/include/app_log.h>

#include <ti/drv/ipc/ipc.h>
#include <ti/osal/SemaphoreP.h>
#include "app_CAN_reader.h"
#include "app_sciclient_helper.h"
#include <ti/sysbios/knl/Task.h>

#include <ti/board/src/j721e_evm/include/board_cfg.h>
#include <ti/board/src/j721e_evm/include/board_pinmux.h>
#include <ti/csl/soc/cslr_soc_ctrl_mmr.h>
#ifdef TIMER_CALL
#include <ti/sysbios/timers/dmtimer/Timer.h>
#include <ti/osal/TimerP.h>
#include <ti/drv/uart/UART_stdio.h>
#include <ti/drv/uart/UART.h>
static uintptr_t SM_addr = NULL;
#endif
static uint32_t FLAG_SM = 0;

static uint8_t gTskTxStackMain[8*1024]
__attribute__ ((section(".bss:taskStackSection")))
__attribute__ ((aligned(8192)))
    ;
static uint8_t gTskRxStackMain[8*1024]
__attribute__ ((section(".bss:taskStackSection")))
__attribute__ ((aligned(8192)));

/* ========================================================================== */
/*                                Macros                                      */
/* ========================================================================== */
#if defined (SOC_AM65XX)
#define APP_ENABLE_UART_PRINT                    (1U)
#elif defined (SOC_J721E)
#define APP_ENABLE_UART_PRINT                    (1U)
#endif

#define APP_MCAN_STD_ID_FILT_START_ADDR          (0U)
#define APP_MCAN_STD_ID_FILTER_NUM               (1U)
#define APP_MCAN_EXT_ID_FILT_START_ADDR          (48U)
#define APP_MCAN_EXT_ID_FILTER_NUM               (1U)
#define APP_MCAN_TX_EVENT_START_ADDR             (100U)
#define APP_MCAN_TX_EVENT_SIZE                   (5U)
#define APP_MCAN_TX_BUFF_START_ADDR              (148U)
#define APP_MCAN_TX_BUFF_SIZE                    (5U)
#define APP_MCAN_TX_FIFO_SIZE                    (5U)
#define APP_MCAN_FIFO_0_START_ADDR               (548U)
#define APP_MCAN_FIFO_0_NUM                      (5U)
#define APP_MCAN_FIFO_1_START_ADDR               (748U)
#define APP_MCAN_FIFO_1_NUM                      (5U)
#define APP_MCAN_RX_BUFF_START_ADDR              (948U)

#define APP_MCAN_EXT_ID_AND_MASK                 (0x1FFFFFFFU)

#define APP_MCU_MCAN_0_INT0                                   (0U)
#define APP_MCU_MCAN_0_INT1                                   (1U)
#define APP_MCU_MCAN_0_TS_INT                                 (4U)
#define APP_MCU_MCAN_1_INT0                                   (2U)
#define APP_MCU_MCAN_1_INT1                                   (3U)
#define APP_MCU_MCAN_1_TS_INT                                 (5U)

#define I2C_BUS_NUM                     (0)
#define TCA6424_SLAVE_ADDR              ((uint8_t) 0x23U)

#define TCA6424_CMD_AUTO_INC            ((uint8_t) 0x80U)

#if defined (SOC_J721E)
#if defined (BUILD_MCU1_0)
#define APP_MAIN_MCAN_2_INT0                (CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0)
#define APP_MAIN_MCAN_2_INT1                (CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_1)
#define APP_MAIN_MCAN_2_TS_INT              (CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_2)
#else
#define APP_MAIN_MCAN_0_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN0_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_0_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN0_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_0_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_2_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN2_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_2_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN2_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_2_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN2_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_4_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN4_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_4_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN4_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_4_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN4_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_5_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN5_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_5_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN5_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_5_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN5_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_6_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN6_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_6_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN6_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_6_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN6_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_7_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN7_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_7_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN7_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_7_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN7_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_9_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN9_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_9_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN9_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_9_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN9_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_11_INT0               (CSLR_R5FSS1_CORE0_INTR_MCAN11_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_11_INT1               (CSLR_R5FSS1_CORE0_INTR_MCAN11_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_11_TS_INT             (CSLR_R5FSS1_CORE0_INTR_MCAN11_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#endif
#endif

/* Print buffer character limit for prints- UART or CCS Console */
#define APP_PRINT_BUFFER_SIZE                       (4000)
#if defined (SOC_AM65XX)
/* Port and pin number mask for GPIO Load pin.
   Bits 7-0: Pin number  and Bits 15-8: Port number */
#define AM65XX_IDK_GPIO_CAN0_STB_PIN    (0x012F)
#define AM65XX_IDK_GPIO_CAN1_STB_PIN    (0x0143)
#endif
#if defined (SOC_J721E)
#define J721E_GPIO_GESI_CAN_STB_PIN     (0x003C)
#define J721E_GPIO_MAIN_MCAN2_STB_PIN   (0x007F)
#endif
/*****************************/
/*****************************/
#define TX_CODE 0
#define RX_CODE 0
#define TX_RX_CODE 1

volatile uint32_t gMcanIsrIntr1Status;
volatile uint32_t num_Tx=0,num_Rx=0,num_ISR=0;
/*****************************/
/*****************************/
/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */
#define APP_USE_CAN
#if defined (APP_USE_CAN)
static pinmuxPerCfg_t gMcan2PinCfg[] =
{
    /* MyMCAN2 -> MCAN2_RX -> AC2 */
    {
        PIN_UART0_CTSN, PIN_MODE(3) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCAN2 -> MCAN2_TX -> AB1 */
    {
        PIN_UART0_RTSN, PIN_MODE(3) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gI2c0PinCfg[] =
{
    /* MyI2C0 -> I2C0_SCL -> AC5 */
    {
        PIN_I2C0_SCL, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    /* MyI2C0 -> I2C0_SDA -> AA5 */
    {
        PIN_I2C0_SDA, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gGpio0PinCfg[] =
{
    /* MyGPIO0 -> GPIO0_127 -> AC4 */
    {
        PIN_UART1_CTSN, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gMcanPinCfg[] =
{
    {0, TRUE, gMcan2PinCfg},
    {1, TRUE, gI2c0PinCfg},
    {2, TRUE, gGpio0PinCfg},
    {PINMUX_END}
};
#endif

static pinmuxBoardCfg_t gCockpitDemoPinmuxDataInfo[] =
{
#if defined (APP_USE_CAN)
    {1, gMcanPinCfg},
#endif
    {PINMUX_END}
};

uint32_t          gMcanAppdataSize[16] =
{0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
volatile uint32_t gMcanIsrIntr0Flag = 1U;
//volatile uint32_t gMcanIsrIntr1Flag = 1U;
SemaphoreP_Handle RxgSyncSem;
SemaphoreP_Handle TxgSyncSem;
MCAN_ECCErrStatus gMcaneccErr;
#define APP_MCAN2_BASEADDR                       (CSL_MCAN2_MSGMEM_RAM_BASE)
uint32_t gMcanModAddr = APP_MCAN2_BASEADDR;

MCAN_TxBufElement          txMsg;
MCAN_RxBufElement    rxMsg;
MCAN_MsgRAMConfigParams    msgRAMConfigParams;
MCAN_ConfigParams          configParams;

const uint32_t mcan2TxMsgId[] = {OBJ_MSG_ID1,OBJ_MSG_ID2,OBJ_MSG_ID3,OBJ_MSG_ID4,OBJ_MSG_ID5,OBJ_MSG_ID6,OBJ_MSG_ID7,OBJ_MSG_ID8,OBJ_MSG_ID9,OBJ_MSG_ID10,OBJ_MSG_ID11,OBJ_MSG_ID12,OBJ_MSG_ID13,OBJ_MSG_ID14,OBJ_MSG_ID15,OBJ_MSG_ID16,OBJ_MSG_ID17,OBJ_MSG_ID18,OBJ_MSG_ID19,OBJ_MSG_ID20,\
                                 OBJ_MSG_ID21,OBJ_MSG_ID22,OBJ_MSG_ID23,OBJ_MSG_ID24,OBJ_MSG_ID25,OBJ_MSG_ID26,OBJ_MSG_ID27,OBJ_MSG_ID28,OBJ_MSG_ID29,OBJ_MSG_ID30,OBJ_MSG_ID31,OBJ_MSG_ID32,OBJ_MSG_ID33,OBJ_MSG_ID34,OBJ_MSG_ID35,OBJ_MSG_ID36,OBJ_MSG_ID37,OBJ_MSG_ID38,OBJ_MSG_ID39,\
                                 OBJ_MSG_ID40,OBJ_MSG_ID41
};



#if defined (SOC_J721E)
/* GPIO Driver board specific pin configuration structure */
GPIO_PinConfig gpioPinConfigs[] = {
    /* Output pin : CAN STB */
    J721E_GPIO_GESI_CAN_STB_PIN   | GPIO_CFG_OUTPUT,
    J721E_GPIO_MAIN_MCAN2_STB_PIN | GPIO_CFG_OUTPUT,
};
#endif

/* GPIO Driver call back functions */
GPIO_CallbackFxn gpioCallbackFunctions[] = {
    NULL
};

/* GPIO Driver configuration structure */
GPIO_v0_Config GPIO_v0_config = {
        gpioPinConfigs,
        gpioCallbackFunctions,
        sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
        sizeof(gpioCallbackFunctions) / sizeof(GPIO_CallbackFxn),
        0,
    };
/* ========================================================================== */
/*                 Internal Function Declarations                             */
/* ========================================================================== */

/**
 * \brief   This function will configure MCAN module
 *
 * \param   none.
 *
 * \retval  status      configuration status.
 */
static int32_t App_mcanConfig(void);

int32_t appRemoteServiceMCAN2Handler(char *service_name, uint32_t cmd,
    void *prm, uint32_t prm_size, uint32_t flags);
/**
 * \brief   This function will configure X-BAR for MCAN interrupts
 *
 * \param   none.
 *
 * \retval  status      configuration status.
 */
static int32_t App_mcanXBarConfig(void);

/**
 * \brief   This is Interrupt Service Routine for MCAN interrupt 0.
 *
 * \param   none.
 *
 * \retval  none.
 */
static void App_mcanIntr01ISR(uintptr_t arg);
/**
 * \brief   This API will load the register from ECC memory bank.
 *
 * \param   txMsg           message object to be transmitted.
 *
 * \return  None.
 */
static int32_t App_mcanRegisterInterrupt(uint32_t intNum, void f(uintptr_t));

/* ========================================================================== */
/*                          Function Definitions                              */
/* ========================================================================== */
#define TCA6424_CMD_AUTO_INC            ((uint8_t) 0x80U)

/* Input status register */
#define TCA6424_REG_INPUT0              ((UInt8) 0x00U)
#define TCA6424_REG_INPUT1              ((UInt8) 0x01U)
#define TCA6424_REG_INPUT2              ((UInt8) 0x02U)

/* Output register to change state of output BIT set to 1, output set HIGH */
#define TCA6424_REG_OUTPUT0             ((uint8_t) 0x04U)
#define TCA6424_REG_OUTPUT1             ((uint8_t) 0x05U)
#define TCA6424_REG_OUTPUT2             ((uint8_t) 0x06U)

/* Configuration register. BIT = '1' sets port to input, BIT = '0' sets
 * port to output */
#define TCA6424_REG_CONFIG0             ((uint8_t) 0x0CU)
#define TCA6424_REG_CONFIG1             ((uint8_t) 0x0DU)
#define TCA6424_REG_CONFIG2             ((uint8_t) 0x0EU)



void SetupI2CTransfer(I2C_Handle handle,  uint32_t slaveAddr,
                      uint8_t *writeData, uint32_t numWriteBytes,
                      uint8_t *readData,  uint32_t numReadBytes)
{
    bool status;
    I2C_Transaction i2cTransaction;

    I2C_transactionInit(&i2cTransaction);
    i2cTransaction.slaveAddress = slaveAddr;
    i2cTransaction.writeBuf = (uint8_t *)&writeData[0];
    i2cTransaction.writeCount = numWriteBytes;
    i2cTransaction.readBuf = (uint8_t *)&readData[0];
    i2cTransaction.readCount = numReadBytes;
    status = I2C_transfer(handle, &i2cTransaction);
    if(FALSE == status)
    {
        UART_printf("\n Data Transfer failed. \n");
    }
}

void padConfig_prcmEnable()
{
    /* UART Init */
    Board_initCfg   boardCfg;
    Board_STATUS    boardStatus;

#if defined (SOC_J721E)
    I2C_Params      i2cParams;
    I2C_Handle      handle = NULL;
    uint8_t         dataToSlave[4];
#endif

    boardCfg = BOARD_INIT_MODULE_CLOCK |
               BOARD_INIT_PINMUX_CONFIG;
#if (APP_ENABLE_UART_PRINT == 1)
    boardCfg |= BOARD_INIT_UART_STDIO;
#endif
    boardStatus = Board_init(boardCfg);
    if (boardStatus != BOARD_SOK)
    {
        UART_printf("[Error] Board init failed!!\n");
    }

    /* Pin mux for CAN STB used in GESI board */
    *(volatile unsigned int *)(0x0011c0f4) = 0x20007;
    /* Pinmux for MAIN_MCAN4 */
    *(volatile unsigned int *)(0x0011c020) = 0x60006;
    *(volatile unsigned int *)(0x0011c024) = 0x60006;
    /* Pinmux for MAIN_MCAN5 */
    *(volatile unsigned int *)(0x0011c04c) = 0x60006;
    *(volatile unsigned int *)(0x0011c050) = 0x60006;
    /* Pinmux for MAIN_MCAN6 */
    *(volatile unsigned int *)(0x0011c054) = 0x60006;
    *(volatile unsigned int *)(0x0011c06C) = 0x60006;
    /* Pinmux for MAIN_MCAN7 */
    *(volatile unsigned int *)(0x0011c074) = 0x60006;
    *(volatile unsigned int *)(0x0011c078) = 0x60006;
    /* Pinmux for MAIN_MCAN9 */
    *(volatile unsigned int *)(0x0011c0cc) = 0x60006;
    *(volatile unsigned int *)(0x0011c0d0) = 0x60006;
    /* Pinmux for MAIN_MCAN11 */
    *(volatile unsigned int *)(0x0011c11c) = 0x60006;
    *(volatile unsigned int *)(0x0011c120) = 0x60006;

    /* GPIO initialization */
    GPIO_init();

    /* Enable CAN transceivers by setting the STB pins */
#if defined (SOC_AM65XX)
    GPIO_write(0, GPIO_PIN_HIGH);
    GPIO_write(1, GPIO_PIN_HIGH);
#elif defined (SOC_J721E)
    /* Enable the TCAN on GESI board.
     * Main Domain MCAN instances 4,5,6,7,9,11.
     */
    GPIO_write(0, GPIO_PIN_LOW);

    /* Enable MCU MCAN 1, WKUP_GPIO0_2. */
    GPIOSetDirMode_v0(CSL_WKUP_GPIO0_BASE, 2, GPIO_DIRECTION_OUTPUT);
    GPIOPinWrite_v0(CSL_WKUP_GPIO0_BASE, 2, GPIO_PIN_LOW);

    /* Enable MCU MCAN 0, WKUP_GPIO0_0, WKUP_GPIO0_54 */
    GPIOSetDirMode_v0(CSL_WKUP_GPIO0_BASE, 0, GPIO_DIRECTION_OUTPUT);
    GPIOPinWrite_v0(CSL_WKUP_GPIO0_BASE, 0, GPIO_PIN_HIGH);
    GPIOSetDirMode_v0(CSL_WKUP_GPIO0_BASE, 54, GPIO_DIRECTION_OUTPUT);
    GPIOPinWrite_v0(CSL_WKUP_GPIO0_BASE, 54, GPIO_PIN_HIGH);

    /* Enable Main MCAN 2, GPIO0_127. */
    GPIO_write(1, GPIO_PIN_LOW);

    /*
     * Configuring TCA6424 IO Exp 2 with addr 0x22
     * This io expander is controlled by i2c0
     * For Main MCAN2 P13 and P14 should be set to 0, This should route the MCAN2 STB line to transciver.
     * For Main MCAN0 P06 and P07 should be set to 1.
     */
    /* I2C initialization */
    I2C_init();
    I2C_Params_init(&i2cParams);
    i2cParams.transferMode = I2C_MODE_BLOCKING;
    i2cParams.bitRate = I2C_400kHz;
    i2cParams.transferCallbackFxn = NULL;

    handle = I2C_open(0U, &i2cParams);
    printf("I2C_open .........\n");

    dataToSlave[0] = TCA6424_REG_CONFIG0 | TCA6424_CMD_AUTO_INC;
    dataToSlave[1] = 0x0U;
    SetupI2CTransfer(handle, 0x23, &dataToSlave[0], 2, NULL, 0);
    printf("SetupI2CTransfer .........\n");

    dataToSlave[0] = TCA6424_REG_INPUT0 | TCA6424_CMD_AUTO_INC;
    dataToSlave[1] = 0x0U;
    dataToSlave[2] = 0x0U;
    dataToSlave[3] = 0x0U;
    SetupI2CTransfer(handle, 0x23, &dataToSlave[0], 1, &dataToSlave[1], 3);

    /* Set P06 and P07 to 1.
     * Set P13 and P14 to 0.
     */
    dataToSlave[0] = TCA6424_REG_OUTPUT0 | TCA6424_CMD_AUTO_INC;
    dataToSlave[1] |= 0xC0;
    dataToSlave[2] &= ~(0x18);
    SetupI2CTransfer(handle, 0x23, &dataToSlave[0], 1, &dataToSlave[1], 3);
#endif
}
#if defined(R5F) && defined(SYSBIOS)
int32_t appMcan2Init(void)
{
    int32_t                    configStatus = CSL_PASS;
    uint32_t                  /* mode         = 0U, */loopCnt = 0U;

    /* Do Pad Config for UART and MCAN */
    padConfig_prcmEnable();

    printf("\n START MCAN2 INIT....\n");

    /* CrossBar Configuration */
    configStatus = App_mcanXBarConfig();

    /* Initialize message to transmit */
    txMsg.id  = (uint32_t)((uint32_t)(0x4U) << 18U);
    txMsg.rtr = 0U;
    txMsg.xtd = 0U;
    txMsg.esi = 0U;
    txMsg.dlc = 0xFU;
    txMsg.brs = 1U;
    txMsg.fdf = 0u;//1U;
    txMsg.efc = 1U;
    txMsg.mm  = 0xAAU;
    for (loopCnt = 0; loopCnt < MCAN_MAX_PAYLOAD_BYTES; loopCnt++)
    {
        txMsg.data[loopCnt] = 0;
    }
    configStatus = App_mcanConfig();

    Rx_Timer_task();
    Tx_Timer_task();

    printf("\n MCAN2 INIT END..........\n");

    return 0;
}
#endif

/* ========================================================================== */
/*                 Internal Function Definitions                              */
/* ========================================================================== */
static int32_t App_mcanRegisterInterrupt(uint32_t intNum, void f(uintptr_t))
{
    int32_t configStatus = STW_SOK;
    OsalRegisterIntrParams_t    intrPrms;
    OsalInterruptRetCode_e      osalRetVal;
    HwiP_Handle                 hwiHandle = NULL;

    /* Enable CPU Interrupts and register ISR - MCAN0 Intr0 */
    Osal_RegisterInterrupt_initParams(&intrPrms);
    /* Populate the interrupt parameters */
    intrPrms.corepacConfig.arg              = (uintptr_t) NULL;
    intrPrms.corepacConfig.isrRoutine       = f;
    intrPrms.corepacConfig.priority         = 0U;
    intrPrms.corepacConfig.corepacEventNum  = 0U;
    intrPrms.corepacConfig.intVecNum        = intNum;

    /* Register interrupts */
    osalRetVal = Osal_RegisterInterrupt(&intrPrms, &hwiHandle);
    if(OSAL_INT_SUCCESS != osalRetVal)
    {
        configStatus = CSL_EFAIL;
    }
    return configStatus;
}

static int32_t App_mcanXBarConfig(void)
{
    int32_t configStatus = STW_SOK;
    /* Main MCAN Inst 2 */
#if TX_CODE
    configStatus =  App_mcanRegisterInterrupt(APP_MAIN_MCAN_2_INT0, &App_mcanIntr0ISR);
#elif RX_CODE
    configStatus = App_mcanRegisterInterrupt (APP_MAIN_MCAN_2_INT1, &App_mcanIntr1ISR);
#else
    configStatus = App_mcanRegisterInterrupt (APP_MAIN_MCAN_2_INT0, &App_mcanIntr01ISR);
#endif
    if(STW_SOK != configStatus)
    {
        UART_printf("CrossBar/Interrupt Configuration failed.\n");
    }
    else
    {
        UART_printf("CrossBar/Interrupt Configuration done.\n");
    }

    return configStatus;
}

static int32_t App_mcanConfig(void)
{
    uint32_t                   fdoe;
    int32_t                    configStatus = CSL_PASS;
    MCAN_RevisionId            revId;
    MCAN_InitParams            initParams;
    MCAN_StdMsgIDFilterElement stdFiltelem;
    MCAN_BitTimingParams       bitTimes;

    /* Initialize MCAN Init params */
#ifdef MCAN_500KBPS
    initParams.fdMode          = 0x0U;
#else
    initParams.fdMode          = 0x1U;
#endif
    initParams.brsEnable       = 0x1U;
    initParams.txpEnable       = 0x0U;
    initParams.efbi            = 0x0U;
    initParams.pxhddisable     = 0x0U;
    initParams.darEnable       = 0x0u;//0x1U;
    initParams.wkupReqEnable   = 0x1U;
    initParams.autoWkupEnable  = 0x1U;
    initParams.emulationEnable = 0x1U;
    initParams.emulationFAck   = 0x0U;
    initParams.clkStopFAck     = 0x0U;
    initParams.wdcPreload      = 0xFFU;
    initParams.tdcEnable       = 0x1U;
    initParams.tdcConfig.tdcf  = 0xAU;
    initParams.tdcConfig.tdco  = 0x6U;
    /* Initialize MCAN Config params */
    configParams.monEnable         = 0x0U;
    configParams.asmEnable         = 0x0U;
    configParams.tsPrescalar       = 0xFU;
    configParams.tsSelect          = 0x0U;
    configParams.timeoutSelect     = MCAN_TIMEOUT_SELECT_CONT;
    configParams.timeoutPreload    = 0xFFFFU;
    configParams.timeoutCntEnable  = 0x0U;
    configParams.filterConfig.rrfs = 0x1U;
    configParams.filterConfig.rrfe = 0x1U;
    configParams.filterConfig.anfe = 0x1U;
    configParams.filterConfig.anfs = 0x1U;
    /* Initialize Message RAM Sections Configuration Parameters */
    msgRAMConfigParams.flssa                = APP_MCAN_STD_ID_FILT_START_ADDR;
    msgRAMConfigParams.lss                  = APP_MCAN_STD_ID_FILTER_NUM;
    msgRAMConfigParams.flesa                = APP_MCAN_EXT_ID_FILT_START_ADDR;
    msgRAMConfigParams.lse                  = APP_MCAN_EXT_ID_FILTER_NUM;
    msgRAMConfigParams.txStartAddr          = APP_MCAN_TX_BUFF_START_ADDR;
    msgRAMConfigParams.txBufNum             = APP_MCAN_TX_BUFF_SIZE;//32
    msgRAMConfigParams.txFIFOSize           = 0U;
    msgRAMConfigParams.txBufMode            = 0U;
    msgRAMConfigParams.txBufElemSize        = MCAN_ELEM_SIZE_64BYTES;//8
    msgRAMConfigParams.txEventFIFOStartAddr = APP_MCAN_TX_EVENT_START_ADDR;
    msgRAMConfigParams.txEventFIFOSize      = 10u;//APP_MCAN_TX_BUFF_SIZE;
    msgRAMConfigParams.txEventFIFOWaterMark = 3U;
    msgRAMConfigParams.rxFIFO0startAddr     = APP_MCAN_FIFO_0_START_ADDR;
    msgRAMConfigParams.rxFIFO0size          = APP_MCAN_FIFO_0_NUM;
    msgRAMConfigParams.rxFIFO0waterMark     = 3U;
    msgRAMConfigParams.rxFIFO0OpMode        = 0U;
    msgRAMConfigParams.rxFIFO1startAddr     = APP_MCAN_FIFO_1_START_ADDR;
    msgRAMConfigParams.rxFIFO1size          = 10;//APP_MCAN_FIFO_1_NUM;
    msgRAMConfigParams.rxFIFO1waterMark     = 3U;
    msgRAMConfigParams.rxFIFO1OpMode        = 0U;
    msgRAMConfigParams.rxBufStartAddr       = APP_MCAN_RX_BUFF_START_ADDR;
    msgRAMConfigParams.rxBufElemSize        = MCAN_ELEM_SIZE_64BYTES;
    msgRAMConfigParams.rxFIFO0ElemSize      = MCAN_ELEM_SIZE_64BYTES;
    msgRAMConfigParams.rxFIFO1ElemSize      = MCAN_ELEM_SIZE_64BYTES;
    /* Initialize Tx Buffer Config params */
    stdFiltelem.sfid2 = 0x0U;
    stdFiltelem.sfid1 = 0x0U;;//0x4U;
    stdFiltelem.sfec  = 0x0U;;//0x7U;
    stdFiltelem.sft   = 0x0U;
    /* Initialize bit timings
     * Configuring 1Mbps and 5Mbps as nominal and data bit-rate respectively */
#ifdef MCAN_500KBPS
    bitTimes.nomRatePrescalar   = 0xFU;
#else
    bitTimes.nomRatePrescalar   = 0x7U;
#endif
    bitTimes.nomTimeSeg1        = 0x5U;
    bitTimes.nomTimeSeg2        = 0x2U;
    bitTimes.nomSynchJumpWidth  = 0x0U;
    bitTimes.dataRatePrescalar  = 0x1U;
    bitTimes.dataTimeSeg1       = 0x3U;
    bitTimes.dataTimeSeg2       = 0x2U;
    bitTimes.dataSynchJumpWidth = 0x0U;

    /* Get MCANSS Revision ID */
    MCAN_getRevisionId(gMcanModAddr, &revId);
    UART_printf("MCANSS Revision ID:\n");
    UART_printf("scheme:0x%x\n", revId.scheme);
    UART_printf("Business Unit:0x%x\n", revId.bu);
    UART_printf("Module ID:0x%x\n", revId.modId);
    UART_printf("RTL Revision:0x%x\n", revId.rtlRev);
    UART_printf("Major Revision:0x%x\n", revId.major);
    UART_printf("Custom Revision:0x%x\n", revId.custom);
    UART_printf("Minor Revision:0x%x\n", revId.minor);
    /* Enable Auto wakeup */
    fdoe = MCAN_isFDOpEnable(gMcanModAddr);
    if ((uint32_t)TRUE == fdoe)
    {
        UART_printf("CAN-FD operation is enabled through E-Fuse.\n");
    }
    else
    {
        UART_printf("CAN-FD operation is disabled through E-Fuse.\n");
    }
    /* wait for memory initialization to happen */
    while (FALSE == MCAN_isMemInitDone(gMcanModAddr))
    {}
    /* Get endianess value */
    UART_printf("Endianess Value: 0x%x\n",
                       MCAN_getEndianVal(gMcanModAddr));
    /* Put MCAN in SW initialization mode */
    MCAN_setOpMode(gMcanModAddr, MCAN_OPERATION_MODE_SW_INIT);
    while (MCAN_OPERATION_MODE_SW_INIT != MCAN_getOpMode(gMcanModAddr))
    {}
    /* Initialize MCAN module */
    MCAN_init(gMcanModAddr, &initParams);
    /* Configure MCAN module */
    MCAN_config(gMcanModAddr, &configParams);
    /* Configure Bit timings */
    MCAN_setBitTime(gMcanModAddr, &bitTimes);
    /* Set Extended ID Mask */
    MCAN_setExtIDAndMask(gMcanModAddr, APP_MCAN_EXT_ID_AND_MASK);
    /* Configure Message RAM Sections */
    MCAN_msgRAMConfig(gMcanModAddr, &msgRAMConfigParams);
    /* Configure Standard ID filter element */
    MCAN_addStdMsgIDFilter(gMcanModAddr, 0U, &stdFiltelem);
    /* Take MCAN out of the SW initialization mode */
    MCAN_setOpMode(gMcanModAddr, MCAN_OPERATION_MODE_NORMAL);
    while (MCAN_OPERATION_MODE_NORMAL != MCAN_getOpMode(gMcanModAddr))
    {}

    /* Enable Interrupts */
    MCAN_enableIntr(gMcanModAddr, MCAN_INTR_MASK_ALL, (uint32_t)TRUE);
    MCAN_enableIntr(gMcanModAddr,
                    MCAN_INTR_SRC_RES_ADDR_ACCESS, (uint32_t)FALSE);

    /* Select Interrupt Line */
    MCAN_selectIntrLine(APP_MCAN2_BASEADDR,
                        MCAN_INTR_MASK_ALL,
                        MCAN_INTR_LINE_NUM_0);

    /* Enable Interrupt Line */
    MCAN_enableIntrLine(APP_MCAN2_BASEADDR,
                        MCAN_INTR_LINE_NUM_0,
                        1U);
    return configStatus;
}

static void App_mcanIntr01ISR(uintptr_t arg)
{
    uint32_t isrType = 2; //set 0 in case of Tx, 1 in case of Rx and 2 is when error interrupt
    gMcanIsrIntr1Status = MCAN_getIntrStatus(gMcanModAddr);
    MCAN_clearIntrStatus(gMcanModAddr, gMcanIsrIntr1Status);
    if (MCAN_INTR_SRC_TRANS_COMPLETE ==
        (gMcanIsrIntr1Status & MCAN_INTR_SRC_TRANS_COMPLETE))
    {
        isrType = 0;
        SemaphoreP_post(TxgSyncSem);
        num_ISR++;
    }

    if(((gMcanIsrIntr1Status & MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ==
         MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ||
       ((gMcanIsrIntr1Status & MCAN_INTR_SRC_RX_FIFO1_NEW_MSG) ==
         MCAN_INTR_SRC_RX_FIFO1_NEW_MSG))
    {
        isrType = 1;
        SemaphoreP_post(RxgSyncSem);
        num_ISR++;
    }
    if(isrType == 2)
    {
        UART_printf("ERROR ISR, Interrupt Status: 0x%x!!\n", gMcanIsrIntr1Status);
    }
}

int32_t appRemoteServiceMcan2Init()
{
    int32_t status = 0;

    status = appRemoteServiceRegister(
        APP_REMOTE_SERVICE_MCAN2_NAME, appRemoteServiceMCAN2Handler);
    if(status!=0)
    {
        UART_printf(
            " REMOTE_SERVICE_MCAN2: ERROR: Unable to register remote service MCAN2 handler\n");
    }
    else
    {
        UART_printf(
                    " REMOTE_SERVICE_MCAN2: Able to register remote service MCAN2 handler\n");
    }
    return status;
}

int32_t appRemoteServiceMcan2DeInit()
{
    int32_t status = 0;

    status = appRemoteServiceUnRegister(APP_REMOTE_SERVICE_MCAN2_NAME);
    if(status!=0)
    {
        UART_printf(
            " REMOTE_SERVICE_MCAN2: ERROR: Unable to register remote service MCAN2 handler\n");
    }

    return status;
}
static void data_sm(UArg arg0, UArg arg1)
{
    int i;
    while(1)
    {
        if(FLAG_SM == 0)
        {
            Task_sleep(333);
            FLAG_SM = 1;
        }
        else
        {
            Task_sleep(33);
        }
        uintptr_t addr = 0xbc7a0000;//jyo - 0xbcb70000;
        int obj = 0;
        appMemCacheInv((void*)addr, sizeof(st_OP_signals)*20);
        st_OP_signals *cmd_prms = (volatile st_OP_signals*)addr;
        printf("status : %d\n",cmd_prms[0].status);
        if(cmd_prms[0].status == STATUS_FILLED)
        {
           for (obj = 0; obj < 20; obj++)
           {
            //Copy all signals
            printf("long dist : %f\t",(cmd_prms[obj].long_distance));
            printf("lat dist : %f\t",(cmd_prms[obj].lat_distance));
            printf("ped_Speed_x : %f\t",(cmd_prms[obj].ped_Speed_y));
            printf("ped_Speed_y : %f\n",(cmd_prms[obj].ped_Speed_x));
           }
           cmd_prms[0].status = STATUS_EMPTY;
        }
        appMemCacheWbInv((void*)addr, sizeof(st_OP_signals)*20);
    }//while
}

int32_t appRemoteServiceMCAN2Handler(char *service_name, uint32_t cmd,
    void *prm, uint32_t prm_size, uint32_t flags)
{
    int32_t  status = CSL_PASS;
    SM_addr = (uintptr_t)(*(volatile uint32_t*)prm);
    printf("ADDRESS OF SHARED MEMORY : R5F = 0x%08x\n",SM_addr);
    return status;
}



#if defined(R5F) && defined(SYSBIOS)
int32_t appMCAN2DeInit()
{
    /* MCAN2_deInit(); */

   return 0;
}
#endif

#ifdef TIMER_CALL
#if (TX_CODE) || (TX_RX_CODE)
void Txtest()
{
   MCAN_ProtocolStatus protStatus;

   st_OP_Signal_1 pd_dcan_msg_final;
   st_OP_Signal_0 pd_dcan_msg;

   uint32_t obj = 0,loopCnt = 0,obj_count = 0;

   /* Enable Transmission interrupt */
   uint32_t status = MCAN_txBufTransIntrEnable(gMcanModAddr,
                                          1U,
                                          (uint32_t)TRUE);
   while(1)
   {
       Task_sleep(33);
#if 1
       if(SM_addr != NULL){
        appMemCacheInv((void*)SM_addr, sizeof(st_OP_signals)*20);
        st_OP_signals *cmd_prms = (volatile st_OP_signals*)SM_addr;
        printf("STATUS: %d\n",cmd_prms[0].status);
#endif
        if(cmd_prms[0].status == STATUS_FILLED)
        {
           for (obj = 0; obj < 5; obj++)
           {
               //Copy all signals
//               printf("long dist : %f\t",(cmd_prms[obj].long_distance));
//               printf("lat dist : %f\t",(cmd_prms[obj].lat_distance));
//               printf("ped_Speed_x : %f\t",(cmd_prms[obj].ped_Speed_y));
//               printf("ped_Speed_y : %f\n",(cmd_prms[obj].ped_Speed_x));

               txMsg.id  = (uint32_t)((uint32_t)(mcan2TxMsgId[obj]) << 18U);

               for (loopCnt = 0; loopCnt < 8; loopCnt++)
               {
                   pd_dcan_msg_final.pd_msg[loopCnt] = 0;
               }
                pd_dcan_msg.dist_x = (cmd_prms[obj].long_distance);
                pd_dcan_msg.dist_y = (cmd_prms[obj].lat_distance);
                pd_dcan_msg.vel_y = (cmd_prms[obj].ped_Speed_y);
                pd_dcan_msg.vel_x = (cmd_prms[obj].ped_Speed_x);
//               pd_dcan_msg.dist_x = 1;
//               pd_dcan_msg.dist_y = 11;
//               pd_dcan_msg.vel_y = 21;
//               pd_dcan_msg.vel_x = 31;

                pd_dcan_msg.obj_type = 5;
                pd_dcan_msg.roll_count = rolling_count;

                //Convert all signals to be signed
                pd_dcan_msg_final.st_PD_Fields.obj_type = pd_dcan_msg.obj_type;
                pd_dcan_msg_final.st_PD_Fields.roll_count = pd_dcan_msg.roll_count;

                pd_dcan_msg_final.st_PD_Fields.dist_x = (pd_dcan_msg.dist_x + 8192);
                pd_dcan_msg_final.st_PD_Fields.vel_x = (pd_dcan_msg.vel_x + 4096);
                pd_dcan_msg_final.st_PD_Fields.dist_y = (pd_dcan_msg.dist_y + 8192);
                pd_dcan_msg_final.st_PD_Fields.vel_y = (pd_dcan_msg.vel_y + 4096);

                for (loopCnt = 0; loopCnt < 8; loopCnt++)
                {
                    txMsg.data[loopCnt] = pd_dcan_msg_final.pd_msg[loopCnt];
                }


               if (CSL_PASS != status)
               {
                   UART_printf("\nError in enabling buffer Transmit interrupt...\n");
               }
               else
               {
                   txMsg.dlc = 8;
                   /* Write message to Msg RAM */
                   MCAN_writeMsgRam(gMcanModAddr,
                                    MCAN_MEM_TYPE_BUF,
                                    1U,
                                    &txMsg);
                   /* Add request for transmission */
                   status = MCAN_txBufAddReq(gMcanModAddr, 1U);
                   if (CSL_PASS != status)
                   {
                       UART_printf("\nError in Adding Transmission Request...\n");
                       break;
                   }
                   //printf("in semaphore pend\n");
                   SemaphoreP_pend(TxgSyncSem, SemaphoreP_WAIT_FOREVER);
                   //printf("out semaphore pend\n");
                   MCAN_getProtocolStatus(gMcanModAddr, &protStatus);

                   /* Checking for Errors */
                   if (((MCAN_ERR_CODE_NO_ERROR == protStatus.lastErrCode) ||
                        (MCAN_ERR_CODE_NO_CHANGE == protStatus.lastErrCode)) &&
                       ((MCAN_ERR_CODE_NO_ERROR == protStatus.dlec) ||
                        (MCAN_ERR_CODE_NO_CHANGE == protStatus.dlec)) &&
                       (0U == protStatus.pxe))
                   {
                    //UART_printf("\nMessage successfully transferred with payload Bytes \n");
                       num_Tx++;
                   }
                   else
                   {
                       UART_printf("\nError in transmission with payload Bytes:%d\n");
                       status = CSL_EFAIL;
                       break;
                   }
               }
           }// for
#if 1
           cmd_prms[0].status = STATUS_EMPTY;
           if(rolling_count==63)
           {
               rolling_count=0;
           }
           else
           {
               rolling_count++;
           }
#endif
        }//if
        appMemCacheWbInv((void*)SM_addr, sizeof(st_OP_signals)*20);}
   }//while
}

#if defined(R5F) && defined(SYSBIOS)
static Void TxMain(UArg arg0, UArg arg1)
{
    UART_printf("Tx thread\n");
    Txtest();
}
static Void RxMain(UArg arg0, UArg arg1)
{
    UART_printf("Rx thread\n");
    Rxtest();
}
void Tx_Timer_task()
{

    printf("TASK SLEEP APPROACH \n");
    uint32_t timePeriodInMilliSec = 33;  //3 sec
    SemaphoreP_Params semParams;

    SemaphoreP_Params_init(&semParams);
    semParams.mode = SemaphoreP_Mode_COUNTING;
    TxgSyncSem = SemaphoreP_create(0U, &semParams);

    Task_Params tskParams1;
   Task_Params_init(&tskParams1);

   tskParams1.arg0 = (UArg) NULL;
   tskParams1.arg1 = (UArg) NULL;
   tskParams1.priority = 8u;
   tskParams1.stack = gTskTxStackMain;
   tskParams1.stackSize = sizeof (gTskTxStackMain);
   Task_create(TxMain, &tskParams1, NULL);

   Task_Params tskParams2;
   Task_Params_init(&tskParams2);

   tskParams2.arg0 = (UArg) NULL;
   tskParams2.arg1 = (UArg) NULL;
   tskParams2.priority = 8u;
   tskParams2.stack = gTskRxStackMain;
   tskParams2.stackSize = sizeof (gTskRxStackMain);
   Task_create(RxMain, &tskParams2, NULL);
   //Task_create(data_sm, &tskParams2, NULL);
}
#endif
#endif

#if (RX_CODE) || (TX_RX_CODE)
#if defined(R5F) && defined(SYSBIOS)
void Rxtest()
{
    int32_t              testStatus = CSL_PASS;
    MCAN_ErrCntStatus    errCounter;
    MCAN_ProtocolStatus protStatus;
    MCAN_RxFIFOStatus fifoStatus;
    while(1)
    {
        SemaphoreP_pend(RxgSyncSem, SemaphoreP_WAIT_FOREVER);

        if(((gMcanIsrIntr1Status & MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ==
                                    MCAN_INTR_SRC_RX_FIFO0_NEW_MSG))
        {
            fifoStatus.num = (uint32_t)MCAN_RX_FIFO_NUM_0;
        }
        else
        {
            fifoStatus.num = (uint32_t)MCAN_RX_FIFO_NUM_1;
        }

        MCAN_getRxFIFOStatus(APP_MCAN2_BASEADDR, &fifoStatus);
        MCAN_readMsgRam(APP_MCAN2_BASEADDR,
                        MCAN_MEM_TYPE_FIFO,
                        fifoStatus.getIdx,
                        (uint32_t)fifoStatus.num,
                        &rxMsg);
        (void) MCAN_writeRxFIFOAck(APP_MCAN2_BASEADDR,
                                   (uint32_t)fifoStatus.num,
                                   fifoStatus.getIdx);

        MCAN_getProtocolStatus(APP_MCAN2_BASEADDR, &protStatus);

       /* Checking for Errors */
       if (((MCAN_ERR_CODE_NO_ERROR == protStatus.lastErrCode) ||
            (MCAN_ERR_CODE_NO_CHANGE == protStatus.lastErrCode)) &&
           ((MCAN_ERR_CODE_NO_ERROR == protStatus.dlec) ||
            (MCAN_ERR_CODE_NO_CHANGE == protStatus.dlec)) &&
           (0U == protStatus.pxe))
       {
//           UART_printf("\n(%dth) Message successfully received.%d , %d, %d ,%d \n",
//                       rxMsg.id,rxMsg.data[0],rxMsg.data[1],rxMsg.data[2],rxMsg.data[3]);
           num_Rx++;
       }
       else
       {
           UART_printf("\nError in reception message.\n");
       }
    }//while
}
void Rx_Timer_task()
{
    int32_t status = CSL_PASS;

    Board_pinmuxUpdate(gCockpitDemoPinmuxDataInfo,
                       BOARD_SOC_DOMAIN_MAIN);

    /* Set drive strength */
    CSL_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE +
            CSL_WKUP_CTRL_MMR_CFG0_H_IO_DRVSTRNGTH0_PROXY, 0xFU);

    CSL_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE +
            CSL_WKUP_CTRL_MMR_CFG0_V_IO_DRVSTRNGTH0_PROXY, 0xFU);

    SET_DEVICE_STATE(TISCI_DEV_MCAN2,
            TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
            status);

    SemaphoreP_Params semParams;

    SemaphoreP_Params_init(&semParams);
    semParams.mode = SemaphoreP_Mode_COUNTING;
    RxgSyncSem = SemaphoreP_create(0U, &semParams);
}
#endif

#endif
#endif

Thanks and Regards

Pooja Krishna

0 Karan Saxena over 4 years ago in reply to Pooja R1

TI__Guru* 75663 points

Hi Pooja,

On #4, I missed that, so you can actually do something like this -

static void App_mcanIntr01ISR(uintptr_t arg)
{
    uint32_t isrType = 2; //set 0 in case of Tx, 1 in case of Rx and 2 is when error interrupt
    uint32_t intrStatus = 0xDEADBEEF;

    intrStatus = MCAN_getIntrStatus(gMcanModAddr);
    gMcanIsrIntr1Status = intrStatus;
    MCAN_clearIntrStatus(gMcanModAddr, intrStatus);

    /* This should happen here */
    num_ISR++;
    
    if (MCAN_INTR_SRC_TRANS_COMPLETE ==
        (intrStatus & MCAN_INTR_SRC_TRANS_COMPLETE))
    {
        isrType = 0;
        SemaphoreP_post(TxgSyncSem);
    }

    if(((intrStatus & MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ==
         MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ||
       ((intrStatus & MCAN_INTR_SRC_RX_FIFO1_NEW_MSG) ==
         MCAN_INTR_SRC_RX_FIFO1_NEW_MSG))
    {
        isrType = 1;    
        SemaphoreP_post(RxgSyncSem);
    }
    if(isrType == 2)
    {
        UART_printf("ERROR ISR, Interrupt Status: 0x%x!!\n", intrStatus);
    }
}

Also, can you please tweak the SemaphoreP_WAIT_FOREVER parameter too?

Regards,

Karan

0 Pooja R1 over 4 years ago in reply to Karan Saxena

Intellectual 790 points

Hello Karan,

1. If we add num_ISR inside App_mcanIntr01ISR(), then num_ISR will keep incrementing with SemaphoreP_WAIT_FOREVER.

2. tweak the SemaphoreP_WAIT_FOREVER parameter too ?

Should I modify the enum "SemaphoreP_WAIT_FOREVER" passed to Rxtest() -> SemaphoreP_pend().PLease clarify on this.

Thanks and Regards

Pooja Krishna

0 Karan Saxena over 4 years ago in reply to Pooja R1

TI__Guru* 75663 points

Hi Pooja,

1. We want to count the total number of ISR, so we can put it there. This would include Tx, Rx and error ISRs.

2. I want you to modify the SemaphoreP_pend(TxgSyncSem, SemaphoreP_WAIT_FOREVER);

The only thing that is bothering me right now is why are we getting the 0x0 ISR status.

Regards,

Karan

0 Karan Saxena over 4 years ago in reply to Karan Saxena

TI__Guru* 75663 points

Hi Pooja,

We want to know which task is working fine after the crash, for this we need the values of the counter at two points after the crash, lets call them T1 and T2.

If in T1 and T2,

If we see that num_Rx increases (Rx task is fine, might not be though)
If we see that num_Tx increases (Tx task is fine, might not be though)
If we see that num_ISR increases (ISR is fine, this should be like this) - the ISR should always hit (due to Rx) even if the tasks are not getting a chance to execute because the CAN Emulator is always sending messages and hence ISR should be triggered due to Rx.

We can also add a global very big array and dump the status of the ISR everytime we hit the ISR, this can give us a picture of what happens when we start the camera app. We can finally look at the array in CCS and check what status we got everytime after the crash happens.

Regards,

Karan

0 Pooja R1 over 4 years ago in reply to Karan Saxena

Intellectual 790 points

Hello Karan,

1. After making changes to App_mcanIntr01ISR , application started running.Also increased the msgRAMConfigParams.rxFIFO1size = 34 to receive more messages.

Also rxFIFO1waterMark value is 3U, should I modify this parameter incase of more messages in Rx side.

2. Also one strange thing is error status ox80u or ox0u keeps coming in UART console and behavior of app at different timestamp is as attached below

Kindly let me know the reason for this behavior.

Thanks and Regards

Pooja Krishna

0 Karan Saxena over 4 years ago in reply to Pooja R1

TI__Guru* 75663 points

Hi Pooja,

Pooja R1 said:
After making changes to App_mcanIntr01ISR , application started running.Also increased the msgRAMConfigParams.rxFIFO1size = 34 to receive more messages.

What do you mean by the application started running? Does it not hang now after starting the camera app?

On changing rxFIFO1waterMark, it won't make a difference as the IP generates an interrupt when the watermark reaches but we are not waiting for the watermark to reach but are draining the messages as and when they come.

2. I don't see 0x80 but 0x8000000 and 0x0 along with a few 0x8800000 and 0x9800000. These would change the PSR register value and it should enter the else case of the error check in the TX and RX thread. Do you see any prints there? You will not be able to capture the correct PSR in case of the error if you look through from CCS. reason being the Auto re transmission is enabled and a successful message going out will clear the PSR register.

Also, please send me the latest source.

Did you verify in case of the hang that which num_Tx, num_Rx and num_ISR continue to increment and which stops?

Regards,

Karan

0 Pooja R1 over 4 years ago in reply to Karan Saxena

Intellectual 790 points

Hi Karan,

1. Now camera based dl demo application is working without hang for more than 30 mins along with MCAN Rx and Tx.

2. Error status is printed in else case of the error check in the TX and RX ISR. We connected via SD boot mode without CCS.

3. Attaching latest source code for reference

8484.app_mcan2.c

/*
 *   Copyright (c) Texas Instruments Incorporated 2016-2019
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

/**
 *  \file     app_mcan2.c
 *
 *  \brief    This file contains MCAN sample code.
 *
 *  \details  MCAN operational mode is set to Classic CAN.
 *
 */

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
#define TIMER_CALL
#include <stdint.h>
#include <stdio.h>
#include <ti/csl/csl_types.h>
#include <ti/csl/soc.h>
#include <ti/csl/hw_types.h>
#include <ti/csl/arch/csl_arch.h>
#include <ti/csl/csl_mcan.h>
#include <ti/drv/uart/UART.h>
#include <ti/drv/uart/UART_stdio.h>
#include <ti/osal/osal.h>
#include <ti/drv/gpio/GPIO.h>
#include <ti/drv/gpio/soc/GPIO_soc.h>
#include <ti/csl/csl_gpio.h>
#include <ti/board/board.h>
#include <ti/drv/i2c/I2C.h>
#if defined (SOC_J721E)
#include <ti/drv/sciclient/sciclient.h>
#endif
#include <utils/mcan/app_mcan2.h>
#include <utils/remote_service/include/app_remote_service.h>
#include <utils/console_io/include/app_log.h>

#include <ti/drv/ipc/ipc.h>
#include <ti/osal/SemaphoreP.h>
#include "app_CAN_reader.h"
#include "app_sciclient_helper.h"
#include <ti/sysbios/knl/Task.h>

#include <ti/board/src/j721e_evm/include/board_cfg.h>
#include <ti/board/src/j721e_evm/include/board_pinmux.h>
#include <ti/csl/soc/cslr_soc_ctrl_mmr.h>
#ifdef TIMER_CALL
#include <ti/sysbios/timers/dmtimer/Timer.h>
#include <ti/osal/TimerP.h>
#include <ti/drv/uart/UART_stdio.h>
#include <ti/drv/uart/UART.h>
static uintptr_t SM_addr = NULL;
#endif
static uint32_t FLAG_SM = 0;

static uint8_t gTskTxStackMain[8*1024]
__attribute__ ((section(".bss:taskStackSection")))
__attribute__ ((aligned(8192)))
    ;
static uint8_t gTskRxStackMain[8*1024]
__attribute__ ((section(".bss:taskStackSection")))
__attribute__ ((aligned(8192)));

/* ========================================================================== */
/*                                Macros                                      */
/* ========================================================================== */
#if defined (SOC_AM65XX)
#define APP_ENABLE_UART_PRINT                    (1U)
#elif defined (SOC_J721E)
#define APP_ENABLE_UART_PRINT                    (1U)
#endif

#define APP_MCAN_STD_ID_FILT_START_ADDR          (0U)
#define APP_MCAN_STD_ID_FILTER_NUM               (1U)
#define APP_MCAN_EXT_ID_FILT_START_ADDR          (48U)
#define APP_MCAN_EXT_ID_FILTER_NUM               (1U)
#define APP_MCAN_TX_EVENT_START_ADDR             (100U)
#define APP_MCAN_TX_EVENT_SIZE                   (5U)
#define APP_MCAN_TX_BUFF_START_ADDR              (148U)
#define APP_MCAN_TX_BUFF_SIZE                    (5U)
#define APP_MCAN_TX_FIFO_SIZE                    (5U)
#define APP_MCAN_FIFO_0_START_ADDR               (548U)
#define APP_MCAN_FIFO_0_NUM                      (5U)
#define APP_MCAN_FIFO_1_START_ADDR               (748U)
#define APP_MCAN_FIFO_1_NUM                      (5U)
#define APP_MCAN_RX_BUFF_START_ADDR              (948U)

#define APP_MCAN_EXT_ID_AND_MASK                 (0x1FFFFFFFU)

#define APP_MCU_MCAN_0_INT0                                   (0U)
#define APP_MCU_MCAN_0_INT1                                   (1U)
#define APP_MCU_MCAN_0_TS_INT                                 (4U)
#define APP_MCU_MCAN_1_INT0                                   (2U)
#define APP_MCU_MCAN_1_INT1                                   (3U)
#define APP_MCU_MCAN_1_TS_INT                                 (5U)

#define I2C_BUS_NUM                     (0)
#define TCA6424_SLAVE_ADDR              ((uint8_t) 0x23U)

#define TCA6424_CMD_AUTO_INC            ((uint8_t) 0x80U)

#if defined (SOC_J721E)
#if defined (BUILD_MCU1_0)
#define APP_MAIN_MCAN_2_INT0                (CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0)
#define APP_MAIN_MCAN_2_INT1                (CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_1)
#define APP_MAIN_MCAN_2_TS_INT              (CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_2)
#else
#define APP_MAIN_MCAN_0_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN0_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_0_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN0_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_0_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_2_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN2_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_2_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN2_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_2_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN2_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_4_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN4_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_4_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN4_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_4_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN4_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_5_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN5_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_5_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN5_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_5_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN5_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_6_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN6_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_6_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN6_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_6_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN6_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_7_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN7_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_7_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN7_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_7_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN7_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_9_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN9_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_9_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN9_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_9_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN9_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_11_INT0               (CSLR_R5FSS1_CORE0_INTR_MCAN11_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_11_INT1               (CSLR_R5FSS1_CORE0_INTR_MCAN11_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_11_TS_INT             (CSLR_R5FSS1_CORE0_INTR_MCAN11_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#endif
#endif

/* Print buffer character limit for prints- UART or CCS Console */
#define APP_PRINT_BUFFER_SIZE                       (4000)
#if defined (SOC_AM65XX)
/* Port and pin number mask for GPIO Load pin.
   Bits 7-0: Pin number  and Bits 15-8: Port number */
#define AM65XX_IDK_GPIO_CAN0_STB_PIN    (0x012F)
#define AM65XX_IDK_GPIO_CAN1_STB_PIN    (0x0143)
#endif
#if defined (SOC_J721E)
#define J721E_GPIO_GESI_CAN_STB_PIN     (0x003C)
#define J721E_GPIO_MAIN_MCAN2_STB_PIN   (0x007F)
#endif
/*****************************/
/*****************************/
#define TX_CODE 0
#define RX_CODE 0
#define TX_RX_CODE 1

volatile uint32_t gMcanIsrIntr1Status;
//volatile uint32_t num_Tx=0,num_Rx=0,num_ISR=0;
/*****************************/
/*****************************/
/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */
#define APP_USE_CAN
#if defined (APP_USE_CAN)
static pinmuxPerCfg_t gMcan2PinCfg[] =
{
    /* MyMCAN2 -> MCAN2_RX -> AC2 */
    {
        PIN_UART0_CTSN, PIN_MODE(3) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCAN2 -> MCAN2_TX -> AB1 */
    {
        PIN_UART0_RTSN, PIN_MODE(3) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gI2c0PinCfg[] =
{
    /* MyI2C0 -> I2C0_SCL -> AC5 */
    {
        PIN_I2C0_SCL, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    /* MyI2C0 -> I2C0_SDA -> AA5 */
    {
        PIN_I2C0_SDA, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gGpio0PinCfg[] =
{
    /* MyGPIO0 -> GPIO0_127 -> AC4 */
    {
        PIN_UART1_CTSN, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gMcanPinCfg[] =
{
    {0, TRUE, gMcan2PinCfg},
    {1, TRUE, gI2c0PinCfg},
    {2, TRUE, gGpio0PinCfg},
    {PINMUX_END}
};
#endif

static pinmuxBoardCfg_t gCockpitDemoPinmuxDataInfo[] =
{
#if defined (APP_USE_CAN)
    {1, gMcanPinCfg},
#endif
    {PINMUX_END}
};

uint32_t          gMcanAppdataSize[16] =
{0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
volatile uint32_t gMcanIsrIntr0Flag = 1U;
//volatile uint32_t gMcanIsrIntr1Flag = 1U;
SemaphoreP_Handle RxgSyncSem;
SemaphoreP_Handle TxgSyncSem;
MCAN_ECCErrStatus gMcaneccErr;
#define APP_MCAN2_BASEADDR                       (CSL_MCAN2_MSGMEM_RAM_BASE)
uint32_t gMcanModAddr = APP_MCAN2_BASEADDR;

MCAN_TxBufElement          txMsg;
MCAN_RxBufElement    rxMsg;
MCAN_MsgRAMConfigParams    msgRAMConfigParams;
MCAN_ConfigParams          configParams;

const uint32_t mcan2TxMsgId[] = {OBJ_MSG_ID1,OBJ_MSG_ID2,OBJ_MSG_ID3,OBJ_MSG_ID4,OBJ_MSG_ID5,OBJ_MSG_ID6,OBJ_MSG_ID7,OBJ_MSG_ID8,OBJ_MSG_ID9,OBJ_MSG_ID10,OBJ_MSG_ID11,OBJ_MSG_ID12,OBJ_MSG_ID13,OBJ_MSG_ID14,OBJ_MSG_ID15,OBJ_MSG_ID16,OBJ_MSG_ID17,OBJ_MSG_ID18,OBJ_MSG_ID19,OBJ_MSG_ID20,\
                                 OBJ_MSG_ID21,OBJ_MSG_ID22,OBJ_MSG_ID23,OBJ_MSG_ID24,OBJ_MSG_ID25,OBJ_MSG_ID26,OBJ_MSG_ID27,OBJ_MSG_ID28,OBJ_MSG_ID29,OBJ_MSG_ID30,OBJ_MSG_ID31,OBJ_MSG_ID32,OBJ_MSG_ID33,OBJ_MSG_ID34,OBJ_MSG_ID35,OBJ_MSG_ID36,OBJ_MSG_ID37,OBJ_MSG_ID38,OBJ_MSG_ID39,\
                                 OBJ_MSG_ID40,OBJ_MSG_ID41
};



#if defined (SOC_J721E)
/* GPIO Driver board specific pin configuration structure */
GPIO_PinConfig gpioPinConfigs[] = {
    /* Output pin : CAN STB */
    J721E_GPIO_GESI_CAN_STB_PIN   | GPIO_CFG_OUTPUT,
    J721E_GPIO_MAIN_MCAN2_STB_PIN | GPIO_CFG_OUTPUT,
};
#endif

/* GPIO Driver call back functions */
GPIO_CallbackFxn gpioCallbackFunctions[] = {
    NULL
};

/* GPIO Driver configuration structure */
GPIO_v0_Config GPIO_v0_config = {
        gpioPinConfigs,
        gpioCallbackFunctions,
        sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
        sizeof(gpioCallbackFunctions) / sizeof(GPIO_CallbackFxn),
        0,
    };
/* ========================================================================== */
/*                 Internal Function Declarations                             */
/* ========================================================================== */

/**
 * \brief   This function will configure MCAN module
 *
 * \param   none.
 *
 * \retval  status      configuration status.
 */
static int32_t App_mcanConfig(void);

int32_t appRemoteServiceMCAN2Handler(char *service_name, uint32_t cmd,
    void *prm, uint32_t prm_size, uint32_t flags);
/**
 * \brief   This function will configure X-BAR for MCAN interrupts
 *
 * \param   none.
 *
 * \retval  status      configuration status.
 */
static int32_t App_mcanXBarConfig(void);

/**
 * \brief   This is Interrupt Service Routine for MCAN interrupt 0.
 *
 * \param   none.
 *
 * \retval  none.
 */
static void App_mcanIntr01ISR(uintptr_t arg);
/**
 * \brief   This API will load the register from ECC memory bank.
 *
 * \param   txMsg           message object to be transmitted.
 *
 * \return  None.
 */
static int32_t App_mcanRegisterInterrupt(uint32_t intNum, void f(uintptr_t));

/* ========================================================================== */
/*                          Function Definitions                              */
/* ========================================================================== */
#define TCA6424_CMD_AUTO_INC            ((uint8_t) 0x80U)

/* Input status register */
#define TCA6424_REG_INPUT0              ((UInt8) 0x00U)
#define TCA6424_REG_INPUT1              ((UInt8) 0x01U)
#define TCA6424_REG_INPUT2              ((UInt8) 0x02U)

/* Output register to change state of output BIT set to 1, output set HIGH */
#define TCA6424_REG_OUTPUT0             ((uint8_t) 0x04U)
#define TCA6424_REG_OUTPUT1             ((uint8_t) 0x05U)
#define TCA6424_REG_OUTPUT2             ((uint8_t) 0x06U)

/* Configuration register. BIT = '1' sets port to input, BIT = '0' sets
 * port to output */
#define TCA6424_REG_CONFIG0             ((uint8_t) 0x0CU)
#define TCA6424_REG_CONFIG1             ((uint8_t) 0x0DU)
#define TCA6424_REG_CONFIG2             ((uint8_t) 0x0EU)



void SetupI2CTransfer(I2C_Handle handle,  uint32_t slaveAddr,
                      uint8_t *writeData, uint32_t numWriteBytes,
                      uint8_t *readData,  uint32_t numReadBytes)
{
    bool status;
    I2C_Transaction i2cTransaction;

    I2C_transactionInit(&i2cTransaction);
    i2cTransaction.slaveAddress = slaveAddr;
    i2cTransaction.writeBuf = (uint8_t *)&writeData[0];
    i2cTransaction.writeCount = numWriteBytes;
    i2cTransaction.readBuf = (uint8_t *)&readData[0];
    i2cTransaction.readCount = numReadBytes;
    status = I2C_transfer(handle, &i2cTransaction);
    if(FALSE == status)
    {
        UART_printf("\n Data Transfer failed. \n");
    }
}

void padConfig_prcmEnable()
{
    /* UART Init */
    Board_initCfg   boardCfg;
    Board_STATUS    boardStatus;

#if defined (SOC_J721E)
    I2C_Params      i2cParams;
    I2C_Handle      handle = NULL;
    uint8_t         dataToSlave[4];
#endif

    boardCfg = BOARD_INIT_MODULE_CLOCK |
               BOARD_INIT_PINMUX_CONFIG;
#if (APP_ENABLE_UART_PRINT == 1)
    boardCfg |= BOARD_INIT_UART_STDIO;
#endif
    boardStatus = Board_init(boardCfg);
    if (boardStatus != BOARD_SOK)
    {
        UART_printf("[Error] Board init failed!!\n");
    }

    /* Pin mux for CAN STB used in GESI board */
    *(volatile unsigned int *)(0x0011c0f4) = 0x20007;
    /* Pinmux for MAIN_MCAN4 */
    *(volatile unsigned int *)(0x0011c020) = 0x60006;
    *(volatile unsigned int *)(0x0011c024) = 0x60006;
    /* Pinmux for MAIN_MCAN5 */
    *(volatile unsigned int *)(0x0011c04c) = 0x60006;
    *(volatile unsigned int *)(0x0011c050) = 0x60006;
    /* Pinmux for MAIN_MCAN6 */
    *(volatile unsigned int *)(0x0011c054) = 0x60006;
    *(volatile unsigned int *)(0x0011c06C) = 0x60006;
    /* Pinmux for MAIN_MCAN7 */
    *(volatile unsigned int *)(0x0011c074) = 0x60006;
    *(volatile unsigned int *)(0x0011c078) = 0x60006;
    /* Pinmux for MAIN_MCAN9 */
    *(volatile unsigned int *)(0x0011c0cc) = 0x60006;
    *(volatile unsigned int *)(0x0011c0d0) = 0x60006;
    /* Pinmux for MAIN_MCAN11 */
    *(volatile unsigned int *)(0x0011c11c) = 0x60006;
    *(volatile unsigned int *)(0x0011c120) = 0x60006;

    /* GPIO initialization */
    GPIO_init();

    /* Enable CAN transceivers by setting the STB pins */
#if defined (SOC_AM65XX)
    GPIO_write(0, GPIO_PIN_HIGH);
    GPIO_write(1, GPIO_PIN_HIGH);
#elif defined (SOC_J721E)
    /* Enable the TCAN on GESI board.
     * Main Domain MCAN instances 4,5,6,7,9,11.
     */
    GPIO_write(0, GPIO_PIN_LOW);

    /* Enable MCU MCAN 1, WKUP_GPIO0_2. */
    GPIOSetDirMode_v0(CSL_WKUP_GPIO0_BASE, 2, GPIO_DIRECTION_OUTPUT);
    GPIOPinWrite_v0(CSL_WKUP_GPIO0_BASE, 2, GPIO_PIN_LOW);

    /* Enable MCU MCAN 0, WKUP_GPIO0_0, WKUP_GPIO0_54 */
    GPIOSetDirMode_v0(CSL_WKUP_GPIO0_BASE, 0, GPIO_DIRECTION_OUTPUT);
    GPIOPinWrite_v0(CSL_WKUP_GPIO0_BASE, 0, GPIO_PIN_HIGH);
    GPIOSetDirMode_v0(CSL_WKUP_GPIO0_BASE, 54, GPIO_DIRECTION_OUTPUT);
    GPIOPinWrite_v0(CSL_WKUP_GPIO0_BASE, 54, GPIO_PIN_HIGH);

    /* Enable Main MCAN 2, GPIO0_127. */
    GPIO_write(1, GPIO_PIN_LOW);

    /*
     * Configuring TCA6424 IO Exp 2 with addr 0x22
     * This io expander is controlled by i2c0
     * For Main MCAN2 P13 and P14 should be set to 0, This should route the MCAN2 STB line to transciver.
     * For Main MCAN0 P06 and P07 should be set to 1.
     */
    /* I2C initialization */
    I2C_init();
    I2C_Params_init(&i2cParams);
    i2cParams.transferMode = I2C_MODE_BLOCKING;
    i2cParams.bitRate = I2C_400kHz;
    i2cParams.transferCallbackFxn = NULL;

    handle = I2C_open(0U, &i2cParams);
    printf("I2C_open .........\n");

    dataToSlave[0] = TCA6424_REG_CONFIG0 | TCA6424_CMD_AUTO_INC;
    dataToSlave[1] = 0x0U;
    SetupI2CTransfer(handle, 0x23, &dataToSlave[0], 2, NULL, 0);
    printf("SetupI2CTransfer .........\n");

    dataToSlave[0] = TCA6424_REG_INPUT0 | TCA6424_CMD_AUTO_INC;
    dataToSlave[1] = 0x0U;
    dataToSlave[2] = 0x0U;
    dataToSlave[3] = 0x0U;
    SetupI2CTransfer(handle, 0x23, &dataToSlave[0], 1, &dataToSlave[1], 3);

    /* Set P06 and P07 to 1.
     * Set P13 and P14 to 0.
     */
    dataToSlave[0] = TCA6424_REG_OUTPUT0 | TCA6424_CMD_AUTO_INC;
    dataToSlave[1] |= 0xC0;
    dataToSlave[2] &= ~(0x18);
    SetupI2CTransfer(handle, 0x23, &dataToSlave[0], 1, &dataToSlave[1], 3);
#endif
}
#if defined(R5F) && defined(SYSBIOS)
int32_t appMcan2Init(void)
{
    int32_t                    configStatus = CSL_PASS;
    uint32_t                  /* mode         = 0U, */loopCnt = 0U;

    /* Do Pad Config for UART and MCAN */
    padConfig_prcmEnable();

    printf("\n START MCAN2 INIT....\n");

    /* CrossBar Configuration */
    configStatus = App_mcanXBarConfig();

    /* Initialize message to transmit */
    txMsg.id  = (uint32_t)((uint32_t)(0x4U) << 18U);
    txMsg.rtr = 0U;
    txMsg.xtd = 0U;
    txMsg.esi = 0U;
    txMsg.dlc = 0xFU;
    txMsg.brs = 1U;
    txMsg.fdf = 0u;//1U;
    txMsg.efc = 1U;
    txMsg.mm  = 0xAAU;
    for (loopCnt = 0; loopCnt < 8; loopCnt++)
    {
        txMsg.data[loopCnt] = 0;
    }
    configStatus = App_mcanConfig();

    Rx_Timer_task();
    Tx_Timer_task();

    printf("\n MCAN2 INIT END..........\n");

    return 0;
}
#endif

/* ========================================================================== */
/*                 Internal Function Definitions                              */
/* ========================================================================== */
static int32_t App_mcanRegisterInterrupt(uint32_t intNum, void f(uintptr_t))
{
    int32_t configStatus = STW_SOK;
    OsalRegisterIntrParams_t    intrPrms;
    OsalInterruptRetCode_e      osalRetVal;
    HwiP_Handle                 hwiHandle = NULL;

    /* Enable CPU Interrupts and register ISR - MCAN0 Intr0 */
    Osal_RegisterInterrupt_initParams(&intrPrms);
    /* Populate the interrupt parameters */
    intrPrms.corepacConfig.arg              = (uintptr_t) NULL;
    intrPrms.corepacConfig.isrRoutine       = f;
    intrPrms.corepacConfig.priority         = 0U;
    intrPrms.corepacConfig.corepacEventNum  = 0U;
    intrPrms.corepacConfig.intVecNum        = intNum;

    /* Register interrupts */
    osalRetVal = Osal_RegisterInterrupt(&intrPrms, &hwiHandle);
    if(OSAL_INT_SUCCESS != osalRetVal)
    {
        configStatus = CSL_EFAIL;
    }
    return configStatus;
}

static int32_t App_mcanXBarConfig(void)
{
    int32_t configStatus = STW_SOK;
    /* Main MCAN Inst 2 */
#if TX_CODE
    configStatus =  App_mcanRegisterInterrupt(APP_MAIN_MCAN_2_INT0, &App_mcanIntr0ISR);
#elif RX_CODE
    configStatus = App_mcanRegisterInterrupt (APP_MAIN_MCAN_2_INT1, &App_mcanIntr1ISR);
#else
    configStatus = App_mcanRegisterInterrupt (APP_MAIN_MCAN_2_INT0, &App_mcanIntr01ISR);
#endif
    if(STW_SOK != configStatus)
    {
        UART_printf("CrossBar/Interrupt Configuration failed.\n");
    }
    else
    {
        UART_printf("CrossBar/Interrupt Configuration done.\n");
    }

    return configStatus;
}

static int32_t App_mcanConfig(void)
{
    uint32_t                   fdoe;
    int32_t                    configStatus = CSL_PASS;
    MCAN_RevisionId            revId;
    MCAN_InitParams            initParams;
    MCAN_StdMsgIDFilterElement stdFiltelem;
    MCAN_BitTimingParams       bitTimes;

    /* Initialize MCAN Init params */
#ifdef MCAN_500KBPS
    initParams.fdMode          = 0x0U;
#else
    initParams.fdMode          = 0x1U;
#endif
    initParams.brsEnable       = 0x1U;
    initParams.txpEnable       = 0x0U;
    initParams.efbi            = 0x0U;
    initParams.pxhddisable     = 0x0U;
    initParams.darEnable       = 0x0u;//0x1U;
    initParams.wkupReqEnable   = 0x1U;
    initParams.autoWkupEnable  = 0x1U;
    initParams.emulationEnable = 0x1U;
    initParams.emulationFAck   = 0x0U;
    initParams.clkStopFAck     = 0x0U;
    initParams.wdcPreload      = 0xFFU;
    initParams.tdcEnable       = 0x1U;
    initParams.tdcConfig.tdcf  = 0xAU;
    initParams.tdcConfig.tdco  = 0x6U;
    /* Initialize MCAN Config params */
    configParams.monEnable         = 0x0U;
    configParams.asmEnable         = 0x0U;
    configParams.tsPrescalar       = 0xFU;
    configParams.tsSelect          = 0x0U;
    configParams.timeoutSelect     = MCAN_TIMEOUT_SELECT_CONT;
    configParams.timeoutPreload    = 0xFFFFU;
    configParams.timeoutCntEnable  = 0x0U;
    configParams.filterConfig.rrfs = 0x1U;
    configParams.filterConfig.rrfe = 0x1U;
    configParams.filterConfig.anfe = 0x1U;
    configParams.filterConfig.anfs = 0x1U;
    /* Initialize Message RAM Sections Configuration Parameters */
    msgRAMConfigParams.flssa                = APP_MCAN_STD_ID_FILT_START_ADDR;
    msgRAMConfigParams.lss                  = APP_MCAN_STD_ID_FILTER_NUM;
    msgRAMConfigParams.flesa                = APP_MCAN_EXT_ID_FILT_START_ADDR;
    msgRAMConfigParams.lse                  = APP_MCAN_EXT_ID_FILTER_NUM;
    msgRAMConfigParams.txStartAddr          = APP_MCAN_TX_BUFF_START_ADDR;
    msgRAMConfigParams.txBufNum             = APP_MCAN_TX_BUFF_SIZE;//32
    msgRAMConfigParams.txFIFOSize           = 0U;
    msgRAMConfigParams.txBufMode            = 0U;
    msgRAMConfigParams.txBufElemSize        = MCAN_ELEM_SIZE_64BYTES;//8
    msgRAMConfigParams.txEventFIFOStartAddr = APP_MCAN_TX_EVENT_START_ADDR;
    msgRAMConfigParams.txEventFIFOSize      = 10u;//APP_MCAN_TX_BUFF_SIZE;
    msgRAMConfigParams.txEventFIFOWaterMark = 3U;
    msgRAMConfigParams.rxFIFO0startAddr     = APP_MCAN_FIFO_0_START_ADDR;
    msgRAMConfigParams.rxFIFO0size          = APP_MCAN_FIFO_0_NUM;
    msgRAMConfigParams.rxFIFO0waterMark     = 3U;
    msgRAMConfigParams.rxFIFO0OpMode        = 0U;
    msgRAMConfigParams.rxFIFO1startAddr     = APP_MCAN_FIFO_1_START_ADDR;
    msgRAMConfigParams.rxFIFO1size          = 34;//APP_MCAN_FIFO_1_NUM;
    msgRAMConfigParams.rxFIFO1waterMark     = 3U;
    msgRAMConfigParams.rxFIFO1OpMode        = 0U;
    msgRAMConfigParams.rxBufStartAddr       = APP_MCAN_RX_BUFF_START_ADDR;
    msgRAMConfigParams.rxBufElemSize        = MCAN_ELEM_SIZE_64BYTES;
    msgRAMConfigParams.rxFIFO0ElemSize      = MCAN_ELEM_SIZE_64BYTES;
    msgRAMConfigParams.rxFIFO1ElemSize      = MCAN_ELEM_SIZE_64BYTES;
    /* Initialize Tx Buffer Config params */
    stdFiltelem.sfid2 = 0x0U;
    stdFiltelem.sfid1 = 0x0U;;//0x4U;
    stdFiltelem.sfec  = 0x0U;;//0x7U;
    stdFiltelem.sft   = 0x0U;
    /* Initialize bit timings
     * Configuring 1Mbps and 5Mbps as nominal and data bit-rate respectively */
#ifdef MCAN_500KBPS
    bitTimes.nomRatePrescalar   = 0xFU;
#else
    bitTimes.nomRatePrescalar   = 0x7U;
#endif
    bitTimes.nomTimeSeg1        = 0x5U;
    bitTimes.nomTimeSeg2        = 0x2U;
    bitTimes.nomSynchJumpWidth  = 0x0U;
    bitTimes.dataRatePrescalar  = 0x1U;
    bitTimes.dataTimeSeg1       = 0x3U;
    bitTimes.dataTimeSeg2       = 0x2U;
    bitTimes.dataSynchJumpWidth = 0x0U;

    /* Get MCANSS Revision ID */
    MCAN_getRevisionId(gMcanModAddr, &revId);
    UART_printf("MCANSS Revision ID:\n");
    UART_printf("scheme:0x%x\n", revId.scheme);
    UART_printf("Business Unit:0x%x\n", revId.bu);
    UART_printf("Module ID:0x%x\n", revId.modId);
    UART_printf("RTL Revision:0x%x\n", revId.rtlRev);
    UART_printf("Major Revision:0x%x\n", revId.major);
    UART_printf("Custom Revision:0x%x\n", revId.custom);
    UART_printf("Minor Revision:0x%x\n", revId.minor);
    /* Enable Auto wakeup */
    fdoe = MCAN_isFDOpEnable(gMcanModAddr);
    if ((uint32_t)TRUE == fdoe)
    {
        UART_printf("CAN-FD operation is enabled through E-Fuse.\n");
    }
    else
    {
        UART_printf("CAN-FD operation is disabled through E-Fuse.\n");
    }
    /* wait for memory initialization to happen */
    while (FALSE == MCAN_isMemInitDone(gMcanModAddr))
    {}
    /* Get endianess value */
    UART_printf("Endianess Value: 0x%x\n",
                       MCAN_getEndianVal(gMcanModAddr));
    /* Put MCAN in SW initialization mode */
    MCAN_setOpMode(gMcanModAddr, MCAN_OPERATION_MODE_SW_INIT);
    while (MCAN_OPERATION_MODE_SW_INIT != MCAN_getOpMode(gMcanModAddr))
    {}
    /* Initialize MCAN module */
    MCAN_init(gMcanModAddr, &initParams);
    /* Configure MCAN module */
    MCAN_config(gMcanModAddr, &configParams);
    /* Configure Bit timings */
    MCAN_setBitTime(gMcanModAddr, &bitTimes);
    /* Set Extended ID Mask */
    MCAN_setExtIDAndMask(gMcanModAddr, APP_MCAN_EXT_ID_AND_MASK);
    /* Configure Message RAM Sections */
    MCAN_msgRAMConfig(gMcanModAddr, &msgRAMConfigParams);
    /* Configure Standard ID filter element */
    MCAN_addStdMsgIDFilter(gMcanModAddr, 0U, &stdFiltelem);
    /* Take MCAN out of the SW initialization mode */
    MCAN_setOpMode(gMcanModAddr, MCAN_OPERATION_MODE_NORMAL);
    while (MCAN_OPERATION_MODE_NORMAL != MCAN_getOpMode(gMcanModAddr))
    {}

    /* Enable Interrupts */
    MCAN_enableIntr(gMcanModAddr, MCAN_INTR_MASK_ALL, (uint32_t)TRUE);
    MCAN_enableIntr(gMcanModAddr,
                    MCAN_INTR_SRC_RES_ADDR_ACCESS, (uint32_t)FALSE);

    /* Select Interrupt Line */
    MCAN_selectIntrLine(APP_MCAN2_BASEADDR,
                        MCAN_INTR_MASK_ALL,
                        MCAN_INTR_LINE_NUM_0);

    /* Enable Interrupt Line */
    MCAN_enableIntrLine(APP_MCAN2_BASEADDR,
                        MCAN_INTR_LINE_NUM_0,
                        1U);
    return configStatus;
}

static void App_mcanIntr01ISR(uintptr_t arg)
{
    uint32_t isrType = 2; //set 0 in case of Tx, 1 in case of Rx and 2 is when error interrupt
    uint32_t intrStatus = 0xDEADBEEF;

    intrStatus = MCAN_getIntrStatus(gMcanModAddr);
    gMcanIsrIntr1Status = intrStatus;
    MCAN_clearIntrStatus(gMcanModAddr, intrStatus);

    /* This should happen here */
    //num_ISR++;

    if (MCAN_INTR_SRC_TRANS_COMPLETE ==
        (intrStatus & MCAN_INTR_SRC_TRANS_COMPLETE))
    {
        isrType = 0;
        SemaphoreP_post(TxgSyncSem);
    }

    if(((intrStatus & MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ==
         MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ||
       ((intrStatus & MCAN_INTR_SRC_RX_FIFO1_NEW_MSG) ==
         MCAN_INTR_SRC_RX_FIFO1_NEW_MSG))
    {
        isrType = 1;
        SemaphoreP_post(RxgSyncSem);
    }
    if(isrType == 2)
    {
        UART_printf("ERROR ISR, Interrupt Status: 0x%x!!\n", intrStatus);
    }
}

int32_t appRemoteServiceMcan2Init()
{
    int32_t status = 0;

    status = appRemoteServiceRegister(
        APP_REMOTE_SERVICE_MCAN2_NAME, appRemoteServiceMCAN2Handler);
    if(status!=0)
    {
        UART_printf(
            " REMOTE_SERVICE_MCAN2: ERROR: Unable to register remote service MCAN2 handler\n");
    }
    else
    {
        UART_printf(
                    " REMOTE_SERVICE_MCAN2: Able to register remote service MCAN2 handler\n");
    }
    return status;
}

int32_t appRemoteServiceMcan2DeInit()
{
    int32_t status = 0;

    status = appRemoteServiceUnRegister(APP_REMOTE_SERVICE_MCAN2_NAME);
    if(status!=0)
    {
        UART_printf(
            " REMOTE_SERVICE_MCAN2: ERROR: Unable to register remote service MCAN2 handler\n");
    }

    return status;
}
static void data_sm(UArg arg0, UArg arg1)
{
    int i;
    while(1)
    {
        if(SM_addr != NULL){
            int obj = 0;
            appMemCacheInv((void*)SM_addr, sizeof(st_OP_signals)*20);
            st_OP_signals *cmd_prms = (volatile st_OP_signals*)SM_addr;
            printf("status : %d\n",cmd_prms[0].status);
            if(cmd_prms[0].status == STATUS_FILLED)
            {
               for (obj = 0; obj < 20; obj++)
               {
                //Copy all signals
                printf("long dist : %f\t",(cmd_prms[obj].long_distance));
                printf("lat dist : %f\t",(cmd_prms[obj].lat_distance));
                printf("ped_Speed_x : %f\t",(cmd_prms[obj].ped_Speed_y));
                printf("ped_Speed_y : %f\n",(cmd_prms[obj].ped_Speed_x));
               }
               cmd_prms[0].status = STATUS_EMPTY;
            }
            appMemCacheWbInv((void*)SM_addr, sizeof(st_OP_signals)*20);
        }
    }//while
}

int32_t appRemoteServiceMCAN2Handler(char *service_name, uint32_t cmd,
    void *prm, uint32_t prm_size, uint32_t flags)
{
    int32_t  status = CSL_PASS;
    SM_addr = (uintptr_t)(*(volatile uint32_t*)prm);
    printf("ADDRESS OF SHARED MEMORY : R5F = 0x%08x\n",SM_addr);
    return status;
}

void Txtest()
{
   MCAN_ProtocolStatus protStatus;

   st_OP_Signal_1 pd_dcan_msg_final;
   st_OP_Signal_0 pd_dcan_msg;
   st_Tracker pd_trk_msg;
   st_meta_data p_meta_data;

   uint32_t obj = 0,loopCnt = 0,obj_count = 0;

   /* Enable Transmission interrupt */
   uint32_t status = MCAN_txBufTransIntrEnable(gMcanModAddr,
                                          1U,
                                          (uint32_t)TRUE);
   while(1)
   {
       Task_sleep(33);
#if 1
       if(SM_addr != NULL){
        appMemCacheInv((void*)SM_addr, sizeof(st_OP_signals)*20);
        st_OP_signals *cmd_prms = (volatile st_OP_signals*)SM_addr;
        //printf("STATUS: %d\n",cmd_prms[0].status);
#endif
        if(cmd_prms[0].status == STATUS_FILLED)
        {
           for (obj = 0; obj < 41; obj++)
           {
               txMsg.id  = (uint32_t)((uint32_t)(mcan2TxMsgId[obj]) << 18U);

               for (loopCnt = 0; loopCnt < 8; loopCnt++)
               {
                   pd_dcan_msg_final.pd_msg[loopCnt] = 0;
               }
               if(obj < 20)
               {
                    pd_dcan_msg.dist_x = (cmd_prms[obj].long_distance);
                    pd_dcan_msg.dist_y = (cmd_prms[obj].lat_distance);
                    pd_dcan_msg.vel_y = (cmd_prms[obj].ped_Speed_y);
                    pd_dcan_msg.vel_x = (cmd_prms[obj].ped_Speed_x);

                    pd_dcan_msg.obj_type = 5;
                    pd_dcan_msg.roll_count = rolling_count;

                    //Convert all signals to be signed
                    pd_dcan_msg_final.st_PD_Fields.obj_type = pd_dcan_msg.obj_type;
                    pd_dcan_msg_final.st_PD_Fields.roll_count = pd_dcan_msg.roll_count;

                    pd_dcan_msg_final.st_PD_Fields.dist_x = (pd_dcan_msg.dist_x + 8192);
                    pd_dcan_msg_final.st_PD_Fields.vel_x = (pd_dcan_msg.vel_x + 4096);
                    pd_dcan_msg_final.st_PD_Fields.dist_y = (pd_dcan_msg.dist_y + 8192);
                    pd_dcan_msg_final.st_PD_Fields.vel_y = (pd_dcan_msg.vel_y + 4096);

                    for (loopCnt = 0; loopCnt < 8; loopCnt++)
                    {
                        txMsg.data[loopCnt] = pd_dcan_msg_final.pd_msg[loopCnt];
                    }
               }
               else if(obj < 40)
               {
                   pd_trk_msg.st_PD_Tracker.B_ID = (cmd_prms[obj_count].tracking_id);
                   pd_trk_msg.st_PD_Tracker.B_Status = (cmd_prms[obj_count].tracking_status);
                   pd_trk_msg.st_PD_Tracker.Ang_Left = 163.83;
                   pd_trk_msg.st_PD_Tracker.Ang_Right = 163.83;
                   pd_trk_msg.st_PD_Tracker.Range_Min_from_cam = 0;
                   pd_trk_msg.st_PD_Tracker.roll_count = rolling_count;
                   obj_count++;
                   for (loopCnt = 0; loopCnt < 8; loopCnt++)
                   {
                       txMsg.data[loopCnt] = pd_trk_msg.pd_msg[loopCnt];
                   }
               }
               else
               {
                  p_meta_data.st_meta_fields.overall_roll_count = rolling_count;
                  p_meta_data.st_meta_fields.availability = 1;
                  p_meta_data.st_meta_fields.num_objects = cmd_prms[0].num_of_objects;
                  p_meta_data.st_meta_fields.stat_latency = cmd_prms[0].frame_latency;
                  p_meta_data.st_meta_fields.stat_Dct = 1;
                  p_meta_data.st_meta_fields.Debug_reserv_00 = 0;
                  p_meta_data.st_meta_fields.Debug_reserv_01 = 0;
                  p_meta_data.st_meta_fields.Debug_reserv_02 = 0;
                  p_meta_data.st_meta_fields.Debug_reserv_03 = 0;
                  p_meta_data.st_meta_fields.Debug_reserv_04 = 0;

                  for (loopCnt = 0; loopCnt < 8; loopCnt++)
                  {
                      txMsg.data[loopCnt] = p_meta_data.pd_msg[loopCnt];
                  }
              }


               if (CSL_PASS != status)
               {
                   UART_printf("\nError in enabling buffer Transmit interrupt...\n");
               }
               else
               {
                   txMsg.dlc = 8;
                   /* Write message to Msg RAM */
                   MCAN_writeMsgRam(gMcanModAddr,
                                    MCAN_MEM_TYPE_BUF,
                                    1U,
                                    &txMsg);
                   /* Add request for transmission */
                   status = MCAN_txBufAddReq(gMcanModAddr, 1U);
                   if (CSL_PASS != status)
                   {
                       UART_printf("\nError in Adding Transmission Request...\n");
                       break;
                   }
                   //printf("in semaphore pend\n");
                   SemaphoreP_pend(TxgSyncSem, SemaphoreP_WAIT_FOREVER);
                   //printf("out semaphore pend\n");
                   MCAN_getProtocolStatus(gMcanModAddr, &protStatus);

                   /* Checking for Errors */
                   if (((MCAN_ERR_CODE_NO_ERROR == protStatus.lastErrCode) ||
                        (MCAN_ERR_CODE_NO_CHANGE == protStatus.lastErrCode)) &&
                       ((MCAN_ERR_CODE_NO_ERROR == protStatus.dlec) ||
                        (MCAN_ERR_CODE_NO_CHANGE == protStatus.dlec)) &&
                       (0U == protStatus.pxe))
                   {
                    //UART_printf("\nMessage successfully transferred with payload Bytes \n");
                       //num_Tx++;
                   }
                   else
                   {
                       UART_printf("\nError in transmission with payload Bytes:%d\n");
                       status = CSL_EFAIL;
                       break;
                   }
               }
           }// for
#if 1
           cmd_prms[0].status = STATUS_EMPTY;
           if(rolling_count==63)
           {
               rolling_count=0;
           }
           else
           {
               rolling_count++;
           }
#endif
        }//if
        appMemCacheWbInv((void*)SM_addr, sizeof(st_OP_signals)*20);}
   }//while
}


static Void TxMain(UArg arg0, UArg arg1)
{
    UART_printf("Tx thread\n");
    Txtest();
}
static Void RxMain(UArg arg0, UArg arg1)
{
    UART_printf("Rx thread\n");
    Rxtest();
}
void Tx_Timer_task()
{

    printf("TASK SLEEP APPROACH \n");
    uint32_t timePeriodInMilliSec = 33;  //3 sec
    SemaphoreP_Params semParams;

    SemaphoreP_Params_init(&semParams);
    semParams.mode = SemaphoreP_Mode_COUNTING;
    TxgSyncSem = SemaphoreP_create(0U, &semParams);

    Task_Params tskParams1;
   Task_Params_init(&tskParams1);

   tskParams1.arg0 = (UArg) NULL;
   tskParams1.arg1 = (UArg) NULL;
   tskParams1.priority = 8u;
   tskParams1.stack = gTskTxStackMain;
   tskParams1.stackSize = sizeof (gTskTxStackMain);
   Task_create(TxMain, &tskParams1, NULL);

   Task_Params tskParams2;
   Task_Params_init(&tskParams2);

   tskParams2.arg0 = (UArg) NULL;
   tskParams2.arg1 = (UArg) NULL;
   tskParams2.priority = 8u;
   tskParams2.stack = gTskRxStackMain;
   tskParams2.stackSize = sizeof (gTskRxStackMain);
   Task_create(RxMain, &tskParams2, NULL);
   //Task_create(data_sm, &tskParams2, NULL);
}

void Rxtest()
{
    int32_t              testStatus = CSL_PASS;
    MCAN_ErrCntStatus    errCounter;
    MCAN_ProtocolStatus protStatus;
    MCAN_RxFIFOStatus fifoStatus;
    while(1)
    {
        SemaphoreP_pend(RxgSyncSem, SemaphoreP_WAIT_FOREVER);

        if(((gMcanIsrIntr1Status & MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ==
                                    MCAN_INTR_SRC_RX_FIFO0_NEW_MSG))
        {
            fifoStatus.num = (uint32_t)MCAN_RX_FIFO_NUM_0;
        }
        else
        {
            fifoStatus.num = (uint32_t)MCAN_RX_FIFO_NUM_1;
        }

        MCAN_getRxFIFOStatus(APP_MCAN2_BASEADDR, &fifoStatus);
        MCAN_readMsgRam(APP_MCAN2_BASEADDR,
                        MCAN_MEM_TYPE_FIFO,
                        fifoStatus.getIdx,
                        (uint32_t)fifoStatus.num,
                        &rxMsg);
        (void) MCAN_writeRxFIFOAck(APP_MCAN2_BASEADDR,
                                   (uint32_t)fifoStatus.num,
                                   fifoStatus.getIdx);

        MCAN_getProtocolStatus(APP_MCAN2_BASEADDR, &protStatus);

       /* Checking for Errors */
       if (((MCAN_ERR_CODE_NO_ERROR == protStatus.lastErrCode) ||
            (MCAN_ERR_CODE_NO_CHANGE == protStatus.lastErrCode)) &&
           ((MCAN_ERR_CODE_NO_ERROR == protStatus.dlec) ||
            (MCAN_ERR_CODE_NO_CHANGE == protStatus.dlec)) &&
           (0U == protStatus.pxe))
       {
//           UART_printf("\n(%dth) Message successfully received.%d , %d, %d ,%d \n",
//                       rxMsg.id,rxMsg.data[0],rxMsg.data[1],rxMsg.data[2],rxMsg.data[3]);
           //num_Rx++;
       }
       else
       {
           UART_printf("\nError in reception message.\n");
       }
    }//while
}
void Rx_Timer_task()
{
    int32_t status = CSL_PASS;

    Board_pinmuxUpdate(gCockpitDemoPinmuxDataInfo,
                       BOARD_SOC_DOMAIN_MAIN);

    /* Set drive strength */
    CSL_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE +
            CSL_WKUP_CTRL_MMR_CFG0_H_IO_DRVSTRNGTH0_PROXY, 0xFU);

    CSL_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE +
            CSL_WKUP_CTRL_MMR_CFG0_V_IO_DRVSTRNGTH0_PROXY, 0xFU);

    SET_DEVICE_STATE(TISCI_DEV_MCAN2,
            TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
            status);

    SemaphoreP_Params semParams;

    SemaphoreP_Params_init(&semParams);
    semParams.mode = SemaphoreP_Mode_COUNTING;
    RxgSyncSem = SemaphoreP_create(0U, &semParams);
}

#if defined(R5F) && defined(SYSBIOS)
int32_t appMCAN2DeInit()
{
    /* MCAN2_deInit(); */

   return 0;
}
#endif

4. Currently experimented with 41 Tx msgs at 33ms and 2 Rx msgs at 10ms and did not observe any hang as of now.

Thanks and Regards

Pooja Krishna

0 Karan Saxena over 4 years ago in reply to Pooja R1

TI__Guru* 75663 points

Hi Pooja,

So what all changes were made after which it started to work fine?

2. What error status got printed? Can you share log? I'm not talking about the ISR error, something from the below should print -

       if (((MCAN_ERR_CODE_NO_ERROR == protStatus.lastErrCode) ||
            (MCAN_ERR_CODE_NO_CHANGE == protStatus.lastErrCode)) &&
           ((MCAN_ERR_CODE_NO_ERROR == protStatus.dlec) ||
            (MCAN_ERR_CODE_NO_CHANGE == protStatus.dlec)) &&
           (0U == protStatus.pxe))
       {
//           UART_printf("\n(%dth) Message successfully received.%d , %d, %d ,%d \n",
//                       rxMsg.id,rxMsg.data[0],rxMsg.data[1],rxMsg.data[2],rxMsg.data[3]);
           //num_Rx++;
       }
       else
       {
           UART_printf("\nError in reception message.\n");
       }

Regards,

Karan

0 Pooja R1 over 4 years ago in reply to Karan Saxena

Intellectual 790 points

Hi Karan,

1. The change suggested in App_mcanIntr01ISR() to make seperate copy for Rxtest() and ISR solved the issue w.r.t Tx and also inorder to receive more messages in Rxtest increased FIFO depth.

2. As of now error are generated only from App_mcanIntr01ISR and not printing error (Error in reception message) incase of Rx failure as mentioned in your above post.

So I would like if we can neglect the error generated in App_mcanIntr01ISR().

Kindly let me know incase of any issues.

Thanks and Regards

Pooja Krishna

0 Karan Saxena over 4 years ago in reply to Pooja R1

TI__Guru* 75663 points

Hi Pooja,

Have you verified that you are getting expected data on the TDA4 (Rx) and also on CANoe (i.e. Tx from TDA4)?

Regards,

Karan

0 Pooja R1 over 4 years ago in reply to Karan Saxena

Intellectual 790 points

Hello Karan,

1. Currently Rx messages are sent after camera application is triggered.

--> Data from TDA4x to CAN (Tx) has been verified.

--> Need to validate the Rx data on board side, I will update once verified.

2. One issue observed here is if I start sending Rx messages before triggering camera application, then Rx keeps running but application does not boot.

Kindly let me know the reason behind this behavior.

Thanks and Regards

Pooja Krishna

0 Pooja R1 over 4 years ago in reply to Pooja R1

Intellectual 790 points

Hi Karan,

Thanks for your continued support and suggestions.

1. Validated data transfer of both Tx and Rx between A72 and MCU2_1. Both are happening without any issues.

2. Now the only problem is w.r.t following scenario:-

-> Enable RX messages from CANOe

-> Trigger dl demo application, then it hangs as below:-

Kindly let me know in case of any issues.

Attached updated mcan2.c file for reference.

0172.app_mcan2.c

/*
 *   Copyright (c) Texas Instruments Incorporated 2016-2019
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

/**
 *  \file     app_mcan2.c
 *
 *  \brief    This file contains MCAN sample code.
 *
 *  \details  MCAN operational mode is set to Classic CAN.
 *
 */

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
#include <stdint.h>
#include <stdio.h>
#include <ti/csl/csl_types.h>
#include <ti/csl/soc.h>
#include <ti/csl/hw_types.h>
#include <ti/csl/arch/csl_arch.h>
#include <ti/csl/csl_mcan.h>
#include <ti/drv/uart/UART.h>
#include <ti/drv/uart/UART_stdio.h>
#include <ti/osal/osal.h>
#include <ti/drv/gpio/GPIO.h>
#include <ti/drv/gpio/soc/GPIO_soc.h>
#include <ti/csl/csl_gpio.h>
#include <ti/board/board.h>
#include <ti/drv/i2c/I2C.h>
#if defined (SOC_J721E)
#include <ti/drv/sciclient/sciclient.h>
#endif
#include <utils/mcan/app_mcan2.h>
#include <utils/remote_service/include/app_remote_service.h>
#include <utils/console_io/include/app_log.h>

#include <ti/drv/ipc/ipc.h>
#include <ti/osal/SemaphoreP.h>
#include "app_sciclient_helper.h"
#include <ti/sysbios/knl/Task.h>

#include <ti/board/src/j721e_evm/include/board_cfg.h>
#include <ti/board/src/j721e_evm/include/board_pinmux.h>
#include <ti/csl/soc/cslr_soc_ctrl_mmr.h>
#include <ti/sysbios/timers/dmtimer/Timer.h>
#include <ti/osal/TimerP.h>
#include <ti/drv/uart/UART_stdio.h>
#include <ti/drv/uart/UART.h>

static uintptr_t SM_addr = NULL;
static uint32_t rolling_count = 0;

static uint8_t gTskTxStackMain[8*1024]
__attribute__ ((section(".bss:taskStackSection")))
__attribute__ ((aligned(8192)))
    ;
static uint8_t gTskRxStackMain[8*1024]
__attribute__ ((section(".bss:taskStackSection")))
__attribute__ ((aligned(8192)));

/* ========================================================================== */
/*                                Macros                                      */
/* ========================================================================== */
#if defined (SOC_AM65XX)
#define APP_ENABLE_UART_PRINT                    (1U)
#elif defined (SOC_J721E)
#define APP_ENABLE_UART_PRINT                    (1U)
#endif

#define APP_MCAN_STD_ID_FILT_START_ADDR          (0U)
#define APP_MCAN_STD_ID_FILTER_NUM               (1U)
#define APP_MCAN_EXT_ID_FILT_START_ADDR          (48U)
#define APP_MCAN_EXT_ID_FILTER_NUM               (1U)
#define APP_MCAN_TX_EVENT_START_ADDR             (100U)
#define APP_MCAN_TX_EVENT_SIZE                   (5U)
#define APP_MCAN_TX_BUFF_START_ADDR              (148U)
#define APP_MCAN_TX_BUFF_SIZE                    (5U)
#define APP_MCAN_TX_FIFO_SIZE                    (5U)
#define APP_MCAN_FIFO_0_START_ADDR               (548U)
#define APP_MCAN_FIFO_0_NUM                      (5U)
#define APP_MCAN_FIFO_1_START_ADDR               (748U)
#define APP_MCAN_FIFO_1_NUM                      (5U)
#define APP_MCAN_RX_BUFF_START_ADDR              (948U)

#define APP_MCAN_EXT_ID_AND_MASK                 (0x1FFFFFFFU)

#define APP_MCU_MCAN_0_INT0                                   (0U)
#define APP_MCU_MCAN_0_INT1                                   (1U)
#define APP_MCU_MCAN_0_TS_INT                                 (4U)
#define APP_MCU_MCAN_1_INT0                                   (2U)
#define APP_MCU_MCAN_1_INT1                                   (3U)
#define APP_MCU_MCAN_1_TS_INT                                 (5U)

#define I2C_BUS_NUM                     (0)
#define TCA6424_SLAVE_ADDR              ((uint8_t) 0x23U)

#define TCA6424_CMD_AUTO_INC            ((uint8_t) 0x80U)

#if defined (SOC_J721E)
#if defined (BUILD_MCU1_0)
#define APP_MAIN_MCAN_2_INT0                (CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0)
#define APP_MAIN_MCAN_2_INT1                (CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_1)
#define APP_MAIN_MCAN_2_TS_INT              (CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_2)
#else
#define APP_MAIN_MCAN_0_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN0_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_0_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN0_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_0_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_2_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN2_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_2_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN2_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_2_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN2_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_4_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN4_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_4_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN4_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_4_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN4_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_5_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN5_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_5_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN5_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_5_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN5_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_6_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN6_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_6_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN6_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_6_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN6_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_7_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN7_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_7_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN7_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_7_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN7_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_9_INT0                (CSLR_R5FSS1_CORE0_INTR_MCAN9_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_9_INT1                (CSLR_R5FSS1_CORE0_INTR_MCAN9_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_9_TS_INT              (CSLR_R5FSS1_CORE0_INTR_MCAN9_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_11_INT0               (CSLR_R5FSS1_CORE0_INTR_MCAN11_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_11_INT1               (CSLR_R5FSS1_CORE0_INTR_MCAN11_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_11_TS_INT             (CSLR_R5FSS1_CORE0_INTR_MCAN11_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#endif
#endif

/* Print buffer character limit for prints- UART or CCS Console */
#define APP_PRINT_BUFFER_SIZE                       (4000)
#if defined (SOC_AM65XX)
/* Port and pin number mask for GPIO Load pin.
   Bits 7-0: Pin number  and Bits 15-8: Port number */
#define AM65XX_IDK_GPIO_CAN0_STB_PIN    (0x012F)
#define AM65XX_IDK_GPIO_CAN1_STB_PIN    (0x0143)
#endif
#if defined (SOC_J721E)
#define J721E_GPIO_GESI_CAN_STB_PIN     (0x003C)
#define J721E_GPIO_MAIN_MCAN2_STB_PIN   (0x007F)
#endif
/*****************************/
/*****************************/
#define TX_CODE 0
#define RX_CODE 0
#define TX_RX_CODE 1

volatile uint32_t gMcanIsrIntr1Status;
/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */
#define APP_USE_CAN
#if defined (APP_USE_CAN)
static pinmuxPerCfg_t gMcan2PinCfg[] =
{
    /* MyMCAN2 -> MCAN2_RX -> AC2 */
    {
        PIN_UART0_CTSN, PIN_MODE(3) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    /* MyMCAN2 -> MCAN2_TX -> AB1 */
    {
        PIN_UART0_RTSN, PIN_MODE(3) | \
        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gI2c0PinCfg[] =
{
    /* MyI2C0 -> I2C0_SCL -> AC5 */
    {
        PIN_I2C0_SCL, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    /* MyI2C0 -> I2C0_SDA -> AA5 */
    {
        PIN_I2C0_SDA, PIN_MODE(0) | \
        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
    },
    {PINMUX_END}
};

static pinmuxPerCfg_t gGpio0PinCfg[] =
{
    /* MyGPIO0 -> GPIO0_127 -> AC4 */
    {
        PIN_UART1_CTSN, PIN_MODE(7) | \
        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
    },
    {PINMUX_END}
};

static pinmuxModuleCfg_t gMcanPinCfg[] =
{
    {0, TRUE, gMcan2PinCfg},
    {1, TRUE, gI2c0PinCfg},
    {2, TRUE, gGpio0PinCfg},
    {PINMUX_END}
};
#endif

static pinmuxBoardCfg_t gCockpitDemoPinmuxDataInfo[] =
{
#if defined (APP_USE_CAN)
    {1, gMcanPinCfg},
#endif
    {PINMUX_END}
};

uint32_t          gMcanAppdataSize[16] =
{0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
volatile uint32_t gMcanIsrIntr0Flag = 1U;
SemaphoreP_Handle RxgSyncSem;
SemaphoreP_Handle TxgSyncSem;
#define APP_MCAN2_BASEADDR                       (CSL_MCAN2_MSGMEM_RAM_BASE)
uint32_t gMcanModAddr = APP_MCAN2_BASEADDR;

MCAN_TxBufElement          txMsg;
MCAN_RxBufElement    rxMsg;
MCAN_MsgRAMConfigParams    msgRAMConfigParams;
MCAN_ConfigParams          configParams;

const uint32_t mcan2TxMsgId[] = {OBJ_MSG_ID1,OBJ_MSG_ID2,OBJ_MSG_ID3,OBJ_MSG_ID4,OBJ_MSG_ID5,OBJ_MSG_ID6,OBJ_MSG_ID7,OBJ_MSG_ID8,OBJ_MSG_ID9,OBJ_MSG_ID10,OBJ_MSG_ID11,OBJ_MSG_ID12,OBJ_MSG_ID13,OBJ_MSG_ID14,OBJ_MSG_ID15,OBJ_MSG_ID16,OBJ_MSG_ID17,OBJ_MSG_ID18,OBJ_MSG_ID19,OBJ_MSG_ID20,\
                                 OBJ_MSG_ID21,OBJ_MSG_ID22,OBJ_MSG_ID23,OBJ_MSG_ID24,OBJ_MSG_ID25,OBJ_MSG_ID26,OBJ_MSG_ID27,OBJ_MSG_ID28,OBJ_MSG_ID29,OBJ_MSG_ID30,OBJ_MSG_ID31,OBJ_MSG_ID32,OBJ_MSG_ID33,OBJ_MSG_ID34,OBJ_MSG_ID35,OBJ_MSG_ID36,OBJ_MSG_ID37,OBJ_MSG_ID38,OBJ_MSG_ID39,\
                                 OBJ_MSG_ID40,OBJ_MSG_ID41
};

#if defined (SOC_J721E)
/* GPIO Driver board specific pin configuration structure */
GPIO_PinConfig gpioPinConfigs[] = {
    /* Output pin : CAN STB */
    J721E_GPIO_GESI_CAN_STB_PIN   | GPIO_CFG_OUTPUT,
    J721E_GPIO_MAIN_MCAN2_STB_PIN | GPIO_CFG_OUTPUT,
};
#endif

/* GPIO Driver call back functions */
GPIO_CallbackFxn gpioCallbackFunctions[] = {
    NULL
};

/* GPIO Driver configuration structure */
GPIO_v0_Config GPIO_v0_config = {
        gpioPinConfigs,
        gpioCallbackFunctions,
        sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
        sizeof(gpioCallbackFunctions) / sizeof(GPIO_CallbackFxn),
        0,
    };
/* ========================================================================== */
/*                 Internal Function Declarations                             */
/* ========================================================================== */

/**
 * \brief   This function will configure MCAN module
 *
 * \param   none.
 *
 * \retval  status      configuration status.
 */
static int32_t App_mcanConfig(void);

int32_t appRemoteServiceMCAN2Handler(char *service_name, uint32_t cmd,
    void *prm, uint32_t prm_size, uint32_t flags);
/**
 * \brief   This function will configure X-BAR for MCAN interrupts
 *
 * \param   none.
 *
 * \retval  status      configuration status.
 */
static int32_t App_mcanXBarConfig(void);

/**
 * \brief   This is Interrupt Service Routine for MCAN interrupt 0.
 *
 * \param   none.
 *
 * \retval  none.
 */
static void App_mcanIntr01ISR(uintptr_t arg);
/**
 * \brief   This API will load the register from ECC memory bank.
 *
 * \param   txMsg           message object to be transmitted.
 *
 * \return  None.
 */
static int32_t App_mcanRegisterInterrupt(uint32_t intNum, void f(uintptr_t));

/* ========================================================================== */
/*                          Function Definitions                              */
/* ========================================================================== */
#define TCA6424_CMD_AUTO_INC            ((uint8_t) 0x80U)

/* Input status register */
#define TCA6424_REG_INPUT0              ((UInt8) 0x00U)
#define TCA6424_REG_INPUT1              ((UInt8) 0x01U)
#define TCA6424_REG_INPUT2              ((UInt8) 0x02U)

/* Output register to change state of output BIT set to 1, output set HIGH */
#define TCA6424_REG_OUTPUT0             ((uint8_t) 0x04U)
#define TCA6424_REG_OUTPUT1             ((uint8_t) 0x05U)
#define TCA6424_REG_OUTPUT2             ((uint8_t) 0x06U)

/* Configuration register. BIT = '1' sets port to input, BIT = '0' sets
 * port to output */
#define TCA6424_REG_CONFIG0             ((uint8_t) 0x0CU)
#define TCA6424_REG_CONFIG1             ((uint8_t) 0x0DU)
#define TCA6424_REG_CONFIG2             ((uint8_t) 0x0EU)



void SetupI2CTransfer(I2C_Handle handle,  uint32_t slaveAddr,
                      uint8_t *writeData, uint32_t numWriteBytes,
                      uint8_t *readData,  uint32_t numReadBytes)
{
    bool status;
    I2C_Transaction i2cTransaction;

    I2C_transactionInit(&i2cTransaction);
    i2cTransaction.slaveAddress = slaveAddr;
    i2cTransaction.writeBuf = (uint8_t *)&writeData[0];
    i2cTransaction.writeCount = numWriteBytes;
    i2cTransaction.readBuf = (uint8_t *)&readData[0];
    i2cTransaction.readCount = numReadBytes;
    status = I2C_transfer(handle, &i2cTransaction);
    if(FALSE == status)
    {
        UART_printf("\n Data Transfer failed. \n");
    }
}

void padConfig_prcmEnable()
{
    /* UART Init */
    Board_initCfg   boardCfg;
    Board_STATUS    boardStatus;

#if defined (SOC_J721E)
    I2C_Params      i2cParams;
    I2C_Handle      handle = NULL;
    uint8_t         dataToSlave[4];
#endif

    boardCfg = BOARD_INIT_MODULE_CLOCK |
               BOARD_INIT_PINMUX_CONFIG;
#if (APP_ENABLE_UART_PRINT == 1)
    boardCfg |= BOARD_INIT_UART_STDIO;
#endif
    boardStatus = Board_init(boardCfg);
    if (boardStatus != BOARD_SOK)
    {
        UART_printf("[Error] Board init failed!!\n");
    }

    /* Pin mux for CAN STB used in GESI board */
    *(volatile unsigned int *)(0x0011c0f4) = 0x20007;
    /* Pinmux for MAIN_MCAN4 */
    *(volatile unsigned int *)(0x0011c020) = 0x60006;
    *(volatile unsigned int *)(0x0011c024) = 0x60006;
    /* Pinmux for MAIN_MCAN5 */
    *(volatile unsigned int *)(0x0011c04c) = 0x60006;
    *(volatile unsigned int *)(0x0011c050) = 0x60006;
    /* Pinmux for MAIN_MCAN6 */
    *(volatile unsigned int *)(0x0011c054) = 0x60006;
    *(volatile unsigned int *)(0x0011c06C) = 0x60006;
    /* Pinmux for MAIN_MCAN7 */
    *(volatile unsigned int *)(0x0011c074) = 0x60006;
    *(volatile unsigned int *)(0x0011c078) = 0x60006;
    /* Pinmux for MAIN_MCAN9 */
    *(volatile unsigned int *)(0x0011c0cc) = 0x60006;
    *(volatile unsigned int *)(0x0011c0d0) = 0x60006;
    /* Pinmux for MAIN_MCAN11 */
    *(volatile unsigned int *)(0x0011c11c) = 0x60006;
    *(volatile unsigned int *)(0x0011c120) = 0x60006;

    /* GPIO initialization */
    GPIO_init();

    /* Enable CAN transceivers by setting the STB pins */
#if defined (SOC_AM65XX)
    GPIO_write(0, GPIO_PIN_HIGH);
    GPIO_write(1, GPIO_PIN_HIGH);
#elif defined (SOC_J721E)
    /* Enable the TCAN on GESI board.
     * Main Domain MCAN instances 4,5,6,7,9,11.
     */
    GPIO_write(0, GPIO_PIN_LOW);

    /* Enable MCU MCAN 1, WKUP_GPIO0_2. */
    GPIOSetDirMode_v0(CSL_WKUP_GPIO0_BASE, 2, GPIO_DIRECTION_OUTPUT);
    GPIOPinWrite_v0(CSL_WKUP_GPIO0_BASE, 2, GPIO_PIN_LOW);

    /* Enable MCU MCAN 0, WKUP_GPIO0_0, WKUP_GPIO0_54 */
    GPIOSetDirMode_v0(CSL_WKUP_GPIO0_BASE, 0, GPIO_DIRECTION_OUTPUT);
    GPIOPinWrite_v0(CSL_WKUP_GPIO0_BASE, 0, GPIO_PIN_HIGH);
    GPIOSetDirMode_v0(CSL_WKUP_GPIO0_BASE, 54, GPIO_DIRECTION_OUTPUT);
    GPIOPinWrite_v0(CSL_WKUP_GPIO0_BASE, 54, GPIO_PIN_HIGH);

    /* Enable Main MCAN 2, GPIO0_127. */
    GPIO_write(1, GPIO_PIN_LOW);

    /*
     * Configuring TCA6424 IO Exp 2 with addr 0x22
     * This io expander is controlled by i2c0
     * For Main MCAN2 P13 and P14 should be set to 0, This should route the MCAN2 STB line to transciver.
     * For Main MCAN0 P06 and P07 should be set to 1.
     */
    /* I2C initialization */
    I2C_init();
    I2C_Params_init(&i2cParams);
    i2cParams.transferMode = I2C_MODE_BLOCKING;
    i2cParams.bitRate = I2C_400kHz;
    i2cParams.transferCallbackFxn = NULL;

    handle = I2C_open(0U, &i2cParams);
    UART_printf("I2C_open .........\n");

    dataToSlave[0] = TCA6424_REG_CONFIG0 | TCA6424_CMD_AUTO_INC;
    dataToSlave[1] = 0x0U;
    SetupI2CTransfer(handle, 0x23, &dataToSlave[0], 2, NULL, 0);
    UART_printf("SetupI2CTransfer 1.........\n");

    dataToSlave[0] = TCA6424_REG_INPUT0 | TCA6424_CMD_AUTO_INC;
    dataToSlave[1] = 0x0U;
    dataToSlave[2] = 0x0U;
    dataToSlave[3] = 0x0U;
    SetupI2CTransfer(handle, 0x23, &dataToSlave[0], 1, &dataToSlave[1], 3);
    UART_printf("SetupI2CTransfer 2.........\n");

    /* Set P06 and P07 to 1.
     * Set P13 and P14 to 0.
     */
    dataToSlave[0] = TCA6424_REG_OUTPUT0 | TCA6424_CMD_AUTO_INC;
    dataToSlave[1] |= 0xC0;
    dataToSlave[2] &= ~(0x18);
    SetupI2CTransfer(handle, 0x23, &dataToSlave[0], 1, &dataToSlave[1], 3);
    UART_printf("SetupI2CTransfer 3.........\n");
#endif
}
#if defined(R5F) && defined(SYSBIOS)
void appMcan2Init(UArg arg0, UArg arg1)
{
    int32_t   configStatus = CSL_PASS;
    uint32_t  loopCnt = 0U;

    /* Do Pad Config for UART and MCAN */
    padConfig_prcmEnable();
    UART_printf("padConfig_prcmEnable\n");

    /* CrossBar Configuration */
    configStatus = App_mcanXBarConfig();
    UART_printf("App_mcanXBarConfig status : %d\n",configStatus);

    /* Initialize message to transmit */
    txMsg.id  = (uint32_t)((uint32_t)(0x4U) << 18U);
    txMsg.rtr = 0U;
    txMsg.xtd = 0U;
    txMsg.esi = 0U;
    txMsg.dlc = 0xFU;
    txMsg.brs = 1U;
    txMsg.fdf = 0u;//1U;
    txMsg.efc = 1U;
    txMsg.mm  = 0xAAU;
    for (loopCnt = 0; loopCnt < 8; loopCnt++)
    {
        txMsg.data[loopCnt] = 0;
    }

    configStatus = App_mcanConfig();
    UART_printf("App_mcanConfig status : %d\n",configStatus);

    Rx_Timer_task();
    Tx_Timer_task();
}
#endif

/* ========================================================================== */
/*                 Internal Function Definitions                              */
/* ========================================================================== */
static int32_t App_mcanRegisterInterrupt(uint32_t intNum, void f(uintptr_t))
{
    int32_t configStatus = STW_SOK;
    OsalRegisterIntrParams_t    intrPrms;
    OsalInterruptRetCode_e      osalRetVal;
    HwiP_Handle                 hwiHandle = NULL;

    /* Enable CPU Interrupts and register ISR - MCAN0 Intr0 */
    Osal_RegisterInterrupt_initParams(&intrPrms);
    /* Populate the interrupt parameters */
    intrPrms.corepacConfig.arg              = (uintptr_t) NULL;
    intrPrms.corepacConfig.isrRoutine       = f;
    intrPrms.corepacConfig.priority         = 0U;
    intrPrms.corepacConfig.corepacEventNum  = 0U;
    intrPrms.corepacConfig.intVecNum        = intNum;

    /* Register interrupts */
    osalRetVal = Osal_RegisterInterrupt(&intrPrms, &hwiHandle);
    if(OSAL_INT_SUCCESS != osalRetVal)
    {
        configStatus = CSL_EFAIL;
    }
    return configStatus;
}

static int32_t App_mcanXBarConfig(void)
{
    int32_t configStatus = STW_SOK;
    /* Main MCAN Inst 2 */
    configStatus = App_mcanRegisterInterrupt (APP_MAIN_MCAN_2_INT0, &App_mcanIntr01ISR);
    if(STW_SOK != configStatus)
    {
        UART_printf("CrossBar/Interrupt Configuration failed.\n");
    }
    else
    {
        UART_printf("CrossBar/Interrupt Configuration done.\n");
    }

    return configStatus;
}

static int32_t App_mcanConfig(void)
{
    uint32_t                   fdoe;
    int32_t                    configStatus = CSL_PASS;
    MCAN_RevisionId            revId;
    MCAN_InitParams            initParams;
    MCAN_StdMsgIDFilterElement stdFiltelem;
    MCAN_BitTimingParams       bitTimes;

    /* Initialize MCAN Init params */
#ifdef MCAN_500KBPS
    initParams.fdMode          = 0x0U;
#else
    initParams.fdMode          = 0x1U;
#endif
    initParams.brsEnable       = 0x1U;
    initParams.txpEnable       = 0x0U;
    initParams.efbi            = 0x0U;
    initParams.pxhddisable     = 0x0U;
    initParams.darEnable       = 0x0u;//0x1U;
    initParams.wkupReqEnable   = 0x1U;
    initParams.autoWkupEnable  = 0x1U;
    initParams.emulationEnable = 0x1U;
    initParams.emulationFAck   = 0x0U;
    initParams.clkStopFAck     = 0x0U;
    initParams.wdcPreload      = 0xFFU;
    initParams.tdcEnable       = 0x1U;
    initParams.tdcConfig.tdcf  = 0xAU;
    initParams.tdcConfig.tdco  = 0x6U;
    /* Initialize MCAN Config params */
    configParams.monEnable         = 0x0U;
    configParams.asmEnable         = 0x0U;
    configParams.tsPrescalar       = 0xFU;
    configParams.tsSelect          = 0x0U;
    configParams.timeoutSelect     = MCAN_TIMEOUT_SELECT_CONT;
    configParams.timeoutPreload    = 0xFFFFU;
    configParams.timeoutCntEnable  = 0x0U;
    configParams.filterConfig.rrfs = 0x1U;
    configParams.filterConfig.rrfe = 0x1U;
    configParams.filterConfig.anfe = 0x1U;
    configParams.filterConfig.anfs = 0x1U;
    /* Initialize Message RAM Sections Configuration Parameters */
    msgRAMConfigParams.flssa                = APP_MCAN_STD_ID_FILT_START_ADDR;
    msgRAMConfigParams.lss                  = APP_MCAN_STD_ID_FILTER_NUM;
    msgRAMConfigParams.flesa                = APP_MCAN_EXT_ID_FILT_START_ADDR;
    msgRAMConfigParams.lse                  = APP_MCAN_EXT_ID_FILTER_NUM;
    msgRAMConfigParams.txStartAddr          = APP_MCAN_TX_BUFF_START_ADDR;
    msgRAMConfigParams.txBufNum             = APP_MCAN_TX_BUFF_SIZE;//32
    msgRAMConfigParams.txFIFOSize           = 0U;
    msgRAMConfigParams.txBufMode            = 0U;
    msgRAMConfigParams.txBufElemSize        = MCAN_ELEM_SIZE_64BYTES;//8
    msgRAMConfigParams.txEventFIFOStartAddr = APP_MCAN_TX_EVENT_START_ADDR;
    msgRAMConfigParams.txEventFIFOSize      = 10u;//APP_MCAN_TX_BUFF_SIZE;
    msgRAMConfigParams.txEventFIFOWaterMark = 3U;
    msgRAMConfigParams.rxFIFO0startAddr     = APP_MCAN_FIFO_0_START_ADDR;
    msgRAMConfigParams.rxFIFO0size          = APP_MCAN_FIFO_0_NUM;
    msgRAMConfigParams.rxFIFO0waterMark     = 3U;
    msgRAMConfigParams.rxFIFO0OpMode        = 0U;
    msgRAMConfigParams.rxFIFO1startAddr     = APP_MCAN_FIFO_1_START_ADDR;
    msgRAMConfigParams.rxFIFO1size          = 34;//APP_MCAN_FIFO_1_NUM;
    msgRAMConfigParams.rxFIFO1waterMark     = 3U;
    msgRAMConfigParams.rxFIFO1OpMode        = 0U;
    msgRAMConfigParams.rxBufStartAddr       = APP_MCAN_RX_BUFF_START_ADDR;
    msgRAMConfigParams.rxBufElemSize        = MCAN_ELEM_SIZE_64BYTES;
    msgRAMConfigParams.rxFIFO0ElemSize      = MCAN_ELEM_SIZE_64BYTES;
    msgRAMConfigParams.rxFIFO1ElemSize      = MCAN_ELEM_SIZE_64BYTES;
    /* Initialize Tx Buffer Config params */
    stdFiltelem.sfid2 = 0x0U;
    stdFiltelem.sfid1 = 0x0U;;//0x4U;
    stdFiltelem.sfec  = 0x0U;;//0x7U;
    stdFiltelem.sft   = 0x0U;
    /* Initialize bit timings
     * Configuring 1Mbps and 5Mbps as nominal and data bit-rate respectively */
#ifdef MCAN_500KBPS
    bitTimes.nomRatePrescalar   = 0xFU;
#else
    bitTimes.nomRatePrescalar   = 0x7U;
#endif
    bitTimes.nomTimeSeg1        = 0x5U;
    bitTimes.nomTimeSeg2        = 0x2U;
    bitTimes.nomSynchJumpWidth  = 0x0U;
    bitTimes.dataRatePrescalar  = 0x1U;
    bitTimes.dataTimeSeg1       = 0x3U;
    bitTimes.dataTimeSeg2       = 0x2U;
    bitTimes.dataSynchJumpWidth = 0x0U;

    /* Get MCANSS Revision ID */
    MCAN_getRevisionId(gMcanModAddr, &revId);
    UART_printf("MCANSS Revision ID:\n");
    UART_printf("scheme:0x%x\n", revId.scheme);
    UART_printf("Business Unit:0x%x\n", revId.bu);
    UART_printf("Module ID:0x%x\n", revId.modId);
    UART_printf("RTL Revision:0x%x\n", revId.rtlRev);
    UART_printf("Major Revision:0x%x\n", revId.major);
    UART_printf("Custom Revision:0x%x\n", revId.custom);
    UART_printf("Minor Revision:0x%x\n", revId.minor);
    /* Enable Auto wakeup */
    fdoe = MCAN_isFDOpEnable(gMcanModAddr);
    if ((uint32_t)TRUE == fdoe)
    {
        UART_printf("CAN-FD operation is enabled through E-Fuse.\n");
    }
    else
    {
        UART_printf("CAN-FD operation is disabled through E-Fuse.\n");
    }
    /* wait for memory initialization to happen */
    while (FALSE == MCAN_isMemInitDone(gMcanModAddr))
    {}
    /* Get endianess value */
    UART_printf("Endianess Value: 0x%x\n",
                       MCAN_getEndianVal(gMcanModAddr));
    /* Put MCAN in SW initialization mode */
    MCAN_setOpMode(gMcanModAddr, MCAN_OPERATION_MODE_SW_INIT);
    while (MCAN_OPERATION_MODE_SW_INIT != MCAN_getOpMode(gMcanModAddr))
    {}
    /* Initialize MCAN module */
    MCAN_init(gMcanModAddr, &initParams);
    /* Configure MCAN module */
    MCAN_config(gMcanModAddr, &configParams);
    /* Configure Bit timings */
    MCAN_setBitTime(gMcanModAddr, &bitTimes);
    /* Set Extended ID Mask */
    MCAN_setExtIDAndMask(gMcanModAddr, APP_MCAN_EXT_ID_AND_MASK);
    /* Configure Message RAM Sections */
    MCAN_msgRAMConfig(gMcanModAddr, &msgRAMConfigParams);
    /* Configure Standard ID filter element */
    MCAN_addStdMsgIDFilter(gMcanModAddr, 0U, &stdFiltelem);
    /* Take MCAN out of the SW initialization mode */
    MCAN_setOpMode(gMcanModAddr, MCAN_OPERATION_MODE_NORMAL);
    while (MCAN_OPERATION_MODE_NORMAL != MCAN_getOpMode(gMcanModAddr))
    {}

    /* Enable Interrupts */
    MCAN_enableIntr(gMcanModAddr, MCAN_INTR_MASK_ALL, (uint32_t)TRUE);
    MCAN_enableIntr(gMcanModAddr,
                    MCAN_INTR_SRC_RES_ADDR_ACCESS, (uint32_t)FALSE);

    /* Select Interrupt Line */
    MCAN_selectIntrLine(APP_MCAN2_BASEADDR,
                        MCAN_INTR_MASK_ALL,
                        MCAN_INTR_LINE_NUM_0);

    /* Enable Interrupt Line */
    MCAN_enableIntrLine(APP_MCAN2_BASEADDR,
                        MCAN_INTR_LINE_NUM_0,
                        1U);
    return configStatus;
}

static void App_mcanIntr01ISR(uintptr_t arg)
{
    uint32_t isrType = 2; //set 0 in case of Tx, 1 in case of Rx and 2 is when error interrupt
    uint32_t intrStatus = 0xDEADBEEF;

    intrStatus = MCAN_getIntrStatus(gMcanModAddr);
    gMcanIsrIntr1Status = intrStatus;
    MCAN_clearIntrStatus(gMcanModAddr, intrStatus);

    /* This should happen here */
    //num_ISR++;

    if (MCAN_INTR_SRC_TRANS_COMPLETE ==
        (intrStatus & MCAN_INTR_SRC_TRANS_COMPLETE))
    {
        isrType = 0;
        SemaphoreP_post(TxgSyncSem);
    }

    if(((intrStatus & MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ==
         MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ||
       ((intrStatus & MCAN_INTR_SRC_RX_FIFO1_NEW_MSG) ==
         MCAN_INTR_SRC_RX_FIFO1_NEW_MSG))
    {
        isrType = 1;
        SemaphoreP_post(RxgSyncSem);
    }
    if(isrType == 2)
    {
        //UART_printf("ERROR ISR, Interrupt Status: 0x%x!!\n", intrStatus);
    }
}

int32_t appRemoteServiceMcan2Init()
{
    int32_t status = 0;

    status = appRemoteServiceRegister(
        APP_REMOTE_SERVICE_MCAN2_NAME, appRemoteServiceMCAN2Handler);
    if(status!=0)
    {
        UART_printf(
            " REMOTE_SERVICE_MCAN2: ERROR: Unable to register remote service MCAN2 handler\n");
    }
    else
    {
        UART_printf(
                    " REMOTE_SERVICE_MCAN2: Able to register remote service MCAN2 handler\n");
    }
    return status;
}

int32_t appRemoteServiceMcan2DeInit()
{
    int32_t status = 0;

    status = appRemoteServiceUnRegister(APP_REMOTE_SERVICE_MCAN2_NAME);
    if(status!=0)
    {
        UART_printf(
            " REMOTE_SERVICE_MCAN2: ERROR: Unable to register remote service MCAN2 handler\n");
    }

    return status;
}

int32_t appRemoteServiceMCAN2Handler(char *service_name, uint32_t cmd,
    void *prm, uint32_t prm_size, uint32_t flags)
{
    int32_t  status = CSL_PASS;
    SM_addr = (uintptr_t)(*(volatile uint32_t*)prm);
    printf("ADDRESS OF SHARED MEMORY : R5F = 0x%08x\n",SM_addr);
    return status;
}

void Txtest()
{
   MCAN_ProtocolStatus protStatus;

   st_OP_Signal_1 pd_dcan_msg_final;
   st_OP_Signal_0 pd_dcan_msg;
   st_Tracker pd_trk_msg;
   st_meta_data p_meta_data;

   uint32_t obj = 0,loopCnt = 0,obj_count = 0;

   /* Enable Transmission interrupt */
   uint32_t status = MCAN_txBufTransIntrEnable(gMcanModAddr,
                                          1U,
                                          (uint32_t)TRUE);
   UART_printf("MCAN_txBufTransIntrEnable : %d\n",status);
   while(1)
   {
       Task_sleep(33);

       if(SM_addr != NULL){
        appMemCacheInv((void*)SM_addr, sizeof(st_cameraDBC));
        st_cameraDBC *cmd_prms = (st_cameraDBC*)SM_addr;

        if(cmd_prms->OP_signals[0].status == STATUS_FILLED)
        {
           for (obj = 0; obj < 41; obj++)
           {
               txMsg.id  = (uint32_t)((uint32_t)(mcan2TxMsgId[obj]) << 18U);

               for (loopCnt = 0; loopCnt < 8; loopCnt++)
               {
                   pd_dcan_msg_final.pd_msg[loopCnt] = 0;
               }
               if(obj < 20)
               {
                    pd_dcan_msg.dist_x = (cmd_prms->OP_signals[obj].long_distance);
                    pd_dcan_msg.dist_y = (cmd_prms->OP_signals[obj].lat_distance);
                    pd_dcan_msg.vel_y = (cmd_prms->OP_signals[obj].ped_Speed_y);
                    pd_dcan_msg.vel_x = (cmd_prms->OP_signals[obj].ped_Speed_x);

                    pd_dcan_msg.obj_type = 5;
                    pd_dcan_msg.roll_count = rolling_count;

                    //Convert all signals to be signed
                    pd_dcan_msg_final.st_PD_Fields.obj_type = pd_dcan_msg.obj_type;
                    pd_dcan_msg_final.st_PD_Fields.roll_count = pd_dcan_msg.roll_count;

                    pd_dcan_msg_final.st_PD_Fields.dist_x = (pd_dcan_msg.dist_x + 8192);
                    pd_dcan_msg_final.st_PD_Fields.vel_x = (pd_dcan_msg.vel_x + 4096);
                    pd_dcan_msg_final.st_PD_Fields.dist_y = (pd_dcan_msg.dist_y + 8192);
                    pd_dcan_msg_final.st_PD_Fields.vel_y = (pd_dcan_msg.vel_y + 4096);

                    for (loopCnt = 0; loopCnt < 8; loopCnt++)
                    {
                        txMsg.data[loopCnt] = pd_dcan_msg_final.pd_msg[loopCnt];
                    }
               }
               else if(obj < 40)
               {
                   pd_trk_msg.st_PD_Tracker.B_ID = (cmd_prms->OP_signals[obj_count].tracking_id);
                   pd_trk_msg.st_PD_Tracker.B_Status = (cmd_prms->OP_signals[obj_count].tracking_status);
                   pd_trk_msg.st_PD_Tracker.Ang_Left = 163.83;
                   pd_trk_msg.st_PD_Tracker.Ang_Right = 163.83;
                   pd_trk_msg.st_PD_Tracker.Range_Min_from_cam = 0;
                   pd_trk_msg.st_PD_Tracker.roll_count = rolling_count;
                   obj_count++;
                   for (loopCnt = 0; loopCnt < 8; loopCnt++)
                   {
                       txMsg.data[loopCnt] = pd_trk_msg.pd_msg[loopCnt];
                   }
               }
               else
               {
                  p_meta_data.st_meta_fields.overall_roll_count = rolling_count;
                  p_meta_data.st_meta_fields.availability = 1;
                  p_meta_data.st_meta_fields.num_objects = cmd_prms->OP_signals[0].num_of_objects;
                  p_meta_data.st_meta_fields.stat_latency = cmd_prms->OP_signals[0].frame_latency;
                  p_meta_data.st_meta_fields.stat_Dct = 1;
                  p_meta_data.st_meta_fields.Debug_reserv_00 = 0;
                  p_meta_data.st_meta_fields.Debug_reserv_01 = 0;
                  p_meta_data.st_meta_fields.Debug_reserv_02 = 0;
                  p_meta_data.st_meta_fields.Debug_reserv_03 = 0;
                  p_meta_data.st_meta_fields.Debug_reserv_04 = 0;

                  for (loopCnt = 0; loopCnt < 8; loopCnt++)
                  {
                      txMsg.data[loopCnt] = p_meta_data.pd_msg[loopCnt];
                  }
              }


               if (CSL_PASS != status)
               {
                   UART_printf("\nError in enabling buffer Transmit interrupt...\n");
               }
               else
               {
                   txMsg.dlc = 8;
                   /* Write message to Msg RAM */
                   MCAN_writeMsgRam(gMcanModAddr,
                                    MCAN_MEM_TYPE_BUF,
                                    1U,
                                    &txMsg);
                   /* Add request for transmission */
                   status = MCAN_txBufAddReq(gMcanModAddr, 1U);
                   if (CSL_PASS != status)
                   {
                       UART_printf("\nError in Adding Transmission Request...\n");
                       break;
                   }

                   SemaphoreP_pend(TxgSyncSem, SemaphoreP_WAIT_FOREVER);

                   MCAN_getProtocolStatus(gMcanModAddr, &protStatus);

                   /* Checking for Errors */
                   if (((MCAN_ERR_CODE_NO_ERROR == protStatus.lastErrCode) ||
                        (MCAN_ERR_CODE_NO_CHANGE == protStatus.lastErrCode)) &&
                       ((MCAN_ERR_CODE_NO_ERROR == protStatus.dlec) ||
                        (MCAN_ERR_CODE_NO_CHANGE == protStatus.dlec)) &&
                       (0U == protStatus.pxe))
                   {
                    //UART_printf("\nMessage successfully transferred with payload Bytes \n");
                       //num_Tx++;
                   }
                   else
                   {
                       UART_printf("\nError in transmission with payload Bytes\n");
                       break;
                   }
               }
           }// for
           cmd_prms->OP_signals[0].status = STATUS_EMPTY;
           if(rolling_count==63)
           {
               rolling_count=0;
           }
           else
           {
               rolling_count++;
           }
        }//if
        appMemCacheWbInv((void*)SM_addr, sizeof(st_OP_signals)*20);}
   }//while
}


static Void TxMain(UArg arg0, UArg arg1)
{
    UART_printf("Tx thread\n");
    Txtest();
}
static Void RxMain(UArg arg0, UArg arg1)
{
    UART_printf("Rx thread\n");
    Rxtest();
}
void Tx_Timer_task()
{
    SemaphoreP_Params semParams;
    SemaphoreP_Params_init(&semParams);
    semParams.mode = SemaphoreP_Mode_COUNTING;
    TxgSyncSem = SemaphoreP_create(0U, &semParams);

    Task_Params tskParams1;
    Task_Params_init(&tskParams1);

    tskParams1.arg0 = (UArg) NULL;
    tskParams1.arg1 = (UArg) NULL;
    tskParams1.priority = 8u;
    tskParams1.stack = gTskTxStackMain;
    tskParams1.stackSize = sizeof (gTskTxStackMain);
    Task_create(TxMain, &tskParams1, NULL);

    Task_Params tskParams2;
    Task_Params_init(&tskParams2);

    tskParams2.arg0 = (UArg) NULL;
    tskParams2.arg1 = (UArg) NULL;
    tskParams2.priority = 8u;
    tskParams2.stack = gTskRxStackMain;
    tskParams2.stackSize = sizeof (gTskRxStackMain);
    Task_create(RxMain, &tskParams2, NULL);
}

void Rxtest()
{
    st_VehMsg_00 pd_VehMsg_00;
    st_VehMsg_01 pd_VehMsg_01;
    MCAN_ProtocolStatus protStatus;
    MCAN_RxFIFOStatus fifoStatus;
    while(1)
    {
        SemaphoreP_pend(RxgSyncSem, SemaphoreP_WAIT_FOREVER);

        if(((gMcanIsrIntr1Status & MCAN_INTR_SRC_RX_FIFO0_NEW_MSG) ==
                                    MCAN_INTR_SRC_RX_FIFO0_NEW_MSG))
        {
            fifoStatus.num = (uint32_t)MCAN_RX_FIFO_NUM_0;
        }
        else
        {
            fifoStatus.num = (uint32_t)MCAN_RX_FIFO_NUM_1;
        }

        MCAN_getRxFIFOStatus(APP_MCAN2_BASEADDR, &fifoStatus);
        MCAN_readMsgRam(APP_MCAN2_BASEADDR,
                        MCAN_MEM_TYPE_FIFO,
                        fifoStatus.getIdx,
                        (uint32_t)fifoStatus.num,
                        &rxMsg);
        (void) MCAN_writeRxFIFOAck(APP_MCAN2_BASEADDR,
                                   (uint32_t)fifoStatus.num,
                                   fifoStatus.getIdx);
        if(SM_addr != NULL){
            appMemCacheInv((void*)SM_addr, sizeof(st_cameraDBC));
            st_cameraDBC *cmd_prms = (st_cameraDBC*)SM_addr;
            if(cmd_prms->OP_signals[9].status == STATUS_EMPTY)
            {
                int i;
                if(rxMsg.id == 494931648)
                {
                    for(i = 0;i<8;i++)
                    {
                        pd_VehMsg_00.pd_msg[i] = rxMsg.data[i];
                    }
                    cmd_prms->s16MDPSAngle = pd_VehMsg_00.stVehMsg00.s16MDPSAngle;
                    cmd_prms->s16RrSpd100kph = pd_VehMsg_00.stVehMsg00.s16RrSpd100kph;
                    cmd_prms->s16YawRate = pd_VehMsg_00.stVehMsg00.s16YawRate;
                    cmd_prms->u8YawRateDiag = pd_VehMsg_00.stVehMsg00.u8YawRateDiag;
                    cmd_prms->u8YawRateStat = pd_VehMsg_00.stVehMsg00.u8YawRateStat;

                    cmd_prms->s16VehT100Deg = 0;
                    cmd_prms->s16VehXmm = 0;
                    cmd_prms->s16VehYmm = 0;

                    //printf("[MCU2_1] : Angle = %f,RrSpd = %f, YawRate = %f, Diag = %f,Stat = %f\n ",cmd_prms->s16MDPSAngle,cmd_prms->s16RrSpd100kph,\
                      //     cmd_prms->s16YawRate,cmd_prms->u8YawRateDiag,cmd_prms->u8YawRateStat);
                }
                else if(rxMsg.id == 495193794)
                {
                    for(i = 0;i<8;i++)
                    {
                        pd_VehMsg_01.pd_msg[i] = rxMsg.data[i];
                    }
                    cmd_prms->s16VehT100Deg = pd_VehMsg_01.stVehMsg01.s16VehT100Deg;
                    cmd_prms->s16VehXmm = pd_VehMsg_01.stVehMsg01.s16VehXmm;
                    cmd_prms->s16VehYmm = pd_VehMsg_01.stVehMsg01.s16VehYmm;

                    cmd_prms->s16MDPSAngle = 0;
                    cmd_prms->s16RrSpd100kph = 0;
                    cmd_prms->s16YawRate = 0;
                    cmd_prms->u8YawRateDiag = 0;
                    cmd_prms->u8YawRateStat = 0;

                    //printf("[MCU2_1] : Deg = %f, Xmm = %f , Ymm = %f\n",cmd_prms->s16VehT100Deg, cmd_prms->s16VehXmm, cmd_prms->s16VehYmm);
                }
                else
                {
                    //do nothing
                }
                cmd_prms->OP_signals[9].status = STATUS_FILLED;
            }
        }

        MCAN_getProtocolStatus(APP_MCAN2_BASEADDR, &protStatus);

       /* Checking for Errors */
       if (((MCAN_ERR_CODE_NO_ERROR == protStatus.lastErrCode) ||
            (MCAN_ERR_CODE_NO_CHANGE == protStatus.lastErrCode)) &&
           ((MCAN_ERR_CODE_NO_ERROR == protStatus.dlec) ||
            (MCAN_ERR_CODE_NO_CHANGE == protStatus.dlec)) &&
           (0U == protStatus.pxe))
       {
//           UART_printf("\n(%dth) Message successfully received.%d , %d, %d ,%d \n",
//                       rxMsg.id,rxMsg.data[0],rxMsg.data[1],rxMsg.data[2],rxMsg.data[3]);
       }
       else
       {
           UART_printf("\nError in reception message.\n");
       }
    }//while
}
void Rx_Timer_task()
{
    int32_t status = CSL_PASS;

    Board_pinmuxUpdate(gCockpitDemoPinmuxDataInfo,
                       BOARD_SOC_DOMAIN_MAIN);

    /* Set drive strength */
    CSL_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE +
            CSL_WKUP_CTRL_MMR_CFG0_H_IO_DRVSTRNGTH0_PROXY, 0xFU);

    CSL_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE +
            CSL_WKUP_CTRL_MMR_CFG0_V_IO_DRVSTRNGTH0_PROXY, 0xFU);

    SET_DEVICE_STATE(TISCI_DEV_MCAN2,
            TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
            status);

    SemaphoreP_Params semParams;

    SemaphoreP_Params_init(&semParams);
    semParams.mode = SemaphoreP_Mode_COUNTING;
    RxgSyncSem = SemaphoreP_create(0U, &semParams);
}

#if defined(R5F) && defined(SYSBIOS)
int32_t appMCAN2DeInit()
{
    /* MCAN2_deInit(); */

   return 0;
}
#endif

Thanks and Regards

Pooja

0 Karan Saxena over 4 years ago in reply to Pooja R1

TI__Guru* 75663 points

Hi Pooja,

The prints are coming from the DL demo? The hang which you mentioned hangs both the CAN communication as well as the DL app?

Can you start a new thread, where we can discuss this DL issue from the experts, and close this one?

Regards,

Karan

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TDA4VM: Asynchronous MCAN2 Rx and Tx along with DL based vision app application