• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 101 subscribers
  • Views 313 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM5708: Enable PCIe PHY 1 TX mode in Linux

Christian Fisahn
Intellectual 330 points
Part Number: AM5708

Hello,

from Linux Kernel 4.4 to 4.14 the PCIe Phy implementation was changed, to use the syscon register.

In the Linux Kernel 4.4, we used the "omap_control_pcie1phy" to set the TX mode, like in this patch: https://patchwork.kernel.org/patch/4121261/

Table 18-1800. CTRL_CORE_SMA_SW_6
+17:16 PCIE_TX_RX_CONTROL PCIe RX and TX control of ACSPCIe. RW 0x0
+0x0: ACSPCIe Power Down Mode
+0x1: ACSPCIe TX Mode
+0x2: ACSPCIe RX
+ */

Also setting the Register 0x4A003C14, raw direct lead to an not bootable device.

How can this be achieved with the current device tree and driver implementation?

Regards,

Christian

  • 0
    TI__Mastermind 23125 points

    Christian, 

    Figure 26-19 in the TRM may be a better reference. Upon patch, we like to verify:

    1. CM_CLKMODE_APLL_PCIE[7]: REFSEL = 0b0;  // APLL reference input clock is from ADPLL
    2. CTRL_CORE_SMA_SW_6[17:16]: PCIE_TX_RX_CONTROL = 0b01; //LJCB output buffers in TX mode

    Also can you confirm your initial system of Kernel 4.14 + patch worked in your system? 

    regards

    Jian