AM5728: What is the maximum data rate on the GPMC bus

Sam Shaw

Part Number: AM5728
Other Parts Discussed in Thread: DRA746

I am trying to find out the maximum access time for GPMC read/write into my ASIC when doing asynchronous address/data multiplexed access to a single register. I have seen experiments on the web that show 200ns cycle time when doing this via software which is what I need (no DMA) and in a loop. I have also seen one post on this forum which says it is equivalent to the timeout which is not the answer to my question (https://e2e.ti.com/support/processors/f/791/t/734014?AM5728-The-maximum-bus-access-period-of-GPMC).

Thank you in advance

over 4 years ago

0 Shiou Mei Huang over 4 years ago

TI__Genius 10180 points

Sam,

Timing information can be found and calculated using equations in the device datasheet. Please reference Section 7.10.2 GPMC/NOR Flash Interface Asynchronous Timing.

Best Regards,

Shiou Mei

0 Sam Shaw over 4 years ago in reply to Shiou Mei Huang

Prodigy 80 points

Hi Shiou and thank you for your response.

The data sheet provides timing on the GPMC bus, but my question is the full cycle time which includes the latencies incurred in the chip for access from the core to the peripheral.

Thank you

0 kcastille over 4 years ago in reply to Sam Shaw

TI__Mastermind 48482 points

Sam,

The DRA746 SoC is a sister device to the AM5728. This appnote gives a glimpse into your question:

Regards,

Kyle

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AM5728: What is the maximum data rate on the GPMC bus