Other Parts Discussed in Thread: DRA746
I am trying to find out the maximum access time for GPMC read/write into my ASIC when doing asynchronous address/data multiplexed access to a single register. I have seen experiments on the web that show 200ns cycle time when doing this via software which is what I need (no DMA) and in a loop. I have also seen one post on this forum which says it is equivalent to the timeout which is not the answer to my question (https://e2e.ti.com/support/processors/f/791/t/734014?AM5728-The-maximum-bus-access-period-of-GPMC).
Thank you in advance