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AM5718: GPMC Boot NOR Flash and Multiple Memory Devices on GPMC

Hafiz Haja
Intellectual 470 points
Part Number: AM5718

Hi,

We are in the design stage of an ARM+DSP based Processor module. We have chosen the SItara Processor AM5718 for our application. It is planned to use parallel NOR as boot flash in non-multiplexed mode configuration. So CS0 of Processor will be used by NOR Flash. In addition to NOR Flash interface to GPMC, we are planning to use a NAND Flash & FPGA using CS1 & CS2 respectively. Using eMMC NAND is restricting to use multiplexed mode NOR boot Flash configuration (as per TRM, if correctly understood). So in multiplexed mode configuration an extra address / data latch IC is required, but we are having module size constraints. So it is planned to interface NAND Flash to GPMC.

GPMC Interface:

CS0 --> Parallel NOR Flash (Boot)

CS1 --> NAND Flash (Storage)

CS2 --> FPGA

Please confirm whether GPMC interface can be used in the above configuration.

Regards

Hafiz 

  • 0
    TI__Genius 10180 points

    Hafiz,

    GPMC supports individual configuration registers for each chip select so you can configure them to support NOR, NAND, and FPGA.  Since you can only interface to one at a time, do make sure this is still applicable for your application.

    Since eMMC uses the upper address bits for GPMC, you are correct if eMMC is used GPMC should be in multiplexed mode.  However, the same number of address bits will still be supported; why will you need an additional address bit?

    Best Regards,

    Shiou Mei