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AM6548: 1V8 Analog power supply current transient during startup

Zoran Dukic
Prodigy 155 points
Part Number: AM6548

Hi,

During HW verification testing on our board with AM6548 we noticed that on 1V8 analog power supply we have an really big current transient. This transient was positioned immediately after the SOC_PORZ goes from active to inactive state. We are using external POR. Snapshot of this measurement with Sitara silicon revision 1 is presented at following figure:

Current peak is at 1.3A.

Snapshot of this measurement with Sitara silicon revision 2 is presented at following figure:

Current peak is at 1.79A. Measurements are taken on two identical boards: one assembled with Sitara SR1 and the other with Sitara SR2.

Just for a reference we had performed the same measurement on the IDK board with Sitara SR1. 

It can be seen that this current transient is very narrow (less than 20us). So, we can cleaned it only by using distributed bypass capacitance. 

Is this normal behavior of 1V8 analog power supply rail current during startup?

Best regards,

Zoran Dukic

  • 0
    TI__Guru 51882 points

    Zoran,

    If it's seen on the IDK as well, then likely it's normal operation.

    How are you measuring current?  Did the peak go away with increased capacitance?  Can you add the rstoutn waveform to one of your scope shots?

    Regards,

    Kyle

  • 0 in reply to kcastille
    Prodigy 155 points

    Hello Kyle,

    Current probe TCP0030  and DPO5104 scope from Tektronix were used. On our board we've added 5x10uF/X7R along the power supply rail distribution on the pcb. With this we've reduced the voltage drop below the threshold of PG  sense input. So, yes, with increased capacitance the peak go away. Without additional capacitors we were able to notice that PG output falls to logic "0" during the period of voltage drop. Btw, on the IDK board the voltage drop is also above the threshold of PG SENSE input but this board uses LDO for generating 1V8 analog and used LDO (LP5912-1.8DRVT) has got PG delay time (Time from VOUT > PG threshold to PG toggling) of 140us. Since voltage drop duration is less than 30us it's not affecting the PG output (i.e. rstoutn).

    Regards,

    Zoran

  • 0 in reply to Zoran Dukic
    TI__Guru 51882 points

    Zoran,

    Considering you are maintaining the voltage levels within the OV/UV range there is no concern from the SoC side, and the current is expected.

    The other thing to check ... Is  the increased cap on the rail within spec for the power source component?

    Regards,

    Kyle

  • 0 in reply to kcastille
    Prodigy 155 points

    Kyle,

    Thanks a lot for your answer. The increased capacitance on the rail is within spec of power supply component. We have simulated power supply with increased capacitance on the output rail. Results are within the output voltage spec. 

    We are concerned that this is just a workaround. Since we don't know the root cause for this analog power supply current peak, we are worried that this behavior can be expected on silicon revisions to come but with unpredictable amplitude. Also, maybe the values of current peak will also vary from device to device depending on process. In that case our workaround becomes quite unreliable. 

    Regards,