TDA4VM: Cannot establish 1Gbps link with Marvell PHY 88E1512

&davinci_mdio {

reset-gpios = <&exp2 15 GPIO_ACTIVE_LOW>; // PHY reset is connected to GPIO pin 15 on GPIO expander 2

reset-delay-us = <10000>; // Minimum reset pulse width during normal operation is 10ms for Marvell 88E1512

phy0: ethernet-phy@0 {

// NOTE: The 'compatible' string is not needed, the PHY framework in Linux will

// probe the PHY based on the vendor ID/Device ID

device_type = "ethernet-phy";

reg = <0>;

};

};

&cpsw_port1 {

phy-mode = "rgmii-id";

phy-handle = <&phy0>;

};

And here is the output of kernel regarding Ethernet and Eth PHY:

root@j7-evm:~# dmesg | grep phy
[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080]
[    0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys).
[    0.654587] libphy: Fixed MDIO Bus: probed
[    0.991417] cdns-torrent-phy 5050000.serdes: 4 lanes, max bit rate 5.400 Gbps
[    1.005363] cdns-pcie-host d000000.pcie: Linked as a consumer to phy-5000000.serdes.0
[    2.194175] cdns-pcie-host d800000.pcie: Linked as a consumer to phy-5010000.serdes.1
[    2.456646] cdns-pcie-host e000000.pcie: Linked as a consumer to phy-5020000.serdes.2
[    4.115629] libphy: 46000000.ethernet: probed
[    4.395962] cdns-ufshcd 4e84000.ufs: clk: phy_clk, rate: 19200000
[    6.870944] cmba cmba0: phys address   = 0x00000000c0400000
[    6.901801] cmba cmba1: phys address   = 0x00000000c0800000
[    6.929468] cmba cmba2: phys address   = 0x00000000c0c00000
[    6.963369] cmba cmba3: phys address   = 0x00000000c1000000
[    6.988819] cmba cmba4: phys address   = 0x00000000c1400000
[    7.012441] cmba cmba5: phys address   = 0x00000000c1800000
[    7.051941] cmba cmba6: phys address   = 0x00000000c1c00000
[    7.900493] Marvell 88E1510 k3-cpsw-mdio:00: attached PHY driver [Marvell 88E1510] (mii_bus:phy_addr=k3-cpsw-mdio:00, irq=POLL)

root@j7-evm:~# dmesg | grep ethernet
[    3.793364] am65-cpsw-nuss 46000000.ethernet: rx-flow-id-base is not set -22
[    3.800414] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA00101, cpsw version 0x6BA80100 Ports: 2
[    3.815397] am65-cpsw-nuss 46000000.ethernet: Failed to request tx dma channel -517
[    3.998696] am65-cpsw-nuss 46000000.ethernet: rx-flow-id-base is not set -22
[    4.005769] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA00101, cpsw version 0x6BA80100 Ports: 2
[    4.023524] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48
[    4.038164] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010a, freq:500000000, add_val:1 pps:1
[    4.047117] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 0.4
[    4.054330] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[    4.107464] am65-cpsw-nuss 46000000.ethernet: davinci mdio revision 9.7, bus freq 1000000
[    4.115629] libphy: 46000000.ethernet: probed
[    4.119985] am65-cpsw-nuss 46000000.ethernet: resetting idled controller
[    9.045678] am65-cpsw-nuss 46000000.ethernet eth0: Link is Down
[   14.165744] am65-cpsw-nuss 46000000.ethernet eth0: Link is Up - 100Mbps/Full - flow control off

Even so the Ethernet card to which our platform is connected supports 1Gbs speeds, we are having issues to recognize that on our platform:

root@j7-evm:~# ethtool eth0
Settings for eth0:
    Supported ports: [ TP MII FIBRE ]
    Supported link modes:   10baseT/Half 10baseT/Full
                            100baseT/Half 100baseT/Full
                            1000baseT/Half 1000baseT/Full
    Supported pause frame use: Symmetric Receive-only
    Supports auto-negotiation: Yes
    Supported FEC modes: Not reported
    Advertised link modes:  10baseT/Half 10baseT/Full
                            100baseT/Half 100baseT/Full
                            1000baseT/Half 1000baseT/Full
    Advertised pause frame use: No
    Advertised auto-negotiation: Yes
    Advertised FEC modes: Not reported
    Link partner advertised link modes:  100baseT/Full
    Link partner advertised pause frame use: No
    Link partner advertised auto-negotiation: Yes
    Link partner advertised FEC modes: Not reported
    Speed: 100Mb/s
    Duplex: Full
    Port: MII
    PHYAD: 0
    Transceiver: internal
    Auto-negotiation: on
    Supports Wake-on: g
    Wake-on: d
    Current message level: 0x00000000 (0)
                   
    Link detected: yes

As it can be seen from ethtool output, we are not detecting advertised link mode on our platform greater than 100Mbps.
We are not having issues with the adapter card used on the other side, as it is working fine when we connect it to the EVA board, here is the output of ethtool on EVA board:

root@j7-evm:~# ethtool eth0
Settings for eth0:
    Supported ports: [ TP MII ]
    Supported link modes:   10baseT/Half 10baseT/Full
                            100baseT/Half 100baseT/Full
                            1000baseT/Half 1000baseT/Full
    Supported pause frame use: Symmetric Receive-only
    Supports auto-negotiation: Yes
    Supported FEC modes: Not reported
    Advertised link modes:  10baseT/Half 10baseT/Full
                            100baseT/Half 100baseT/Full
                            1000baseT/Half 1000baseT/Full
    Advertised pause frame use: No
    Advertised auto-negotiation: Yes
    Advertised FEC modes: Not reported
    Link partner advertised link modes:  100baseT/Full
                                         1000baseT/Full
    Link partner advertised pause frame use: No
    Link partner advertised auto-negotiation: Yes
    Link partner advertised FEC modes: Not reported
    Speed: 1000Mb/s
    Duplex: Full
    Port: MII
    PHYAD: 0
    Transceiver: internal
    Auto-negotiation: on
    Supports Wake-on: d
    Wake-on: d
    Current message level: 0x00000000 (0)
                   
    Link detected: yes

Eva board have no issues to detect that Ethernet adapter card on the other side supports 1000Mbps link mode, and have no issues to establish that link speed.

Can you notice any issues we might have so far?

Now, regarding the clocking, we noticed that TDA4 is not supplying the necessary 125MHz clock on MCU_RGMII1_TXC pin for PHY to properly work in RGMII mode, but 25MHz as it was configured on EVA board. We could not find anywhere how to change that clock, nor the PLL setings for MCU_PLL2_HSDIV0_CLKOUT.

Can you help us to resolve this issue?

Regards.

Uros