Hi,
According to the C667x data sheet, TSIP supports only 32.768/16.384/8.192 Mbps bit rates. Is it possible to use TSIP also with 2.048 Mbps and 2.048 MHz clock?
We have a custom board with an E1 framer than can output only 2.048 MHz recovered receive E1 clock, and if 2.048 MHz is not supported, this frequency should be multiplied with a PLL to for example 8.192 MHz. We have an FPGA between the E1 framer and the DSP, but minimum input frequency of the FPGA PLL is 5 MHz, so it is not possible to raise the frequency with the PLL.
Operation at 2.048 MHz would be the perfect solution to this problem. What is your comment?
Regards,
Aarne