TMS320C6678: CVDD problem for SmartReflex function

Anyone please check.

Hi Downey

Have you measured the CVDD close to the failing DSP to see what the device is actually seeing? 

How many boards have you built and with how many are you seeing such issues?

Regards

Mukul 

Downey,

You state that a previous design did not use Smart Reflex.  That is not valid.  Use of Smart Reflex is mandatory for this device as it is required to prevent the device from overheating.

There are many E2E posts related to this topic.  Here is one to get you started:

e2e.ti.com/.../732932

Please use CCS to extract the VCNTLID from each of the DSPs.  The VID value is readable from the VCNTLID register at 0235_0014h and extracted from bits 21:16.  Please refer to the PSC User Guide for the full register definition and the device Data Manual for the full address map.  Once you have all 4 VCNTLID values known, please post them.  Also please provide the exact part number for the devices on your board.

You state that the DSPs are sending VID code [000000].  That is not possible in a production device.  How did you determine this was the value presented?  If you captured this on a scope picture after releasing reset to the C6678, please attach scope captures showing the VID output.

How many boards have you built and with how many are you seeing such issues?

Tom

Hi Tom,

We captured VID status and attached. UCD9244 config file is also attached.

Please review.

6678_VID & UCD9244_config.zip

They made 4 boards and 100% occurred.

Thanks

Downey Kim.

Downey,

Your UCD configuration is not what I need to see.  Please provide the other items requested.

Tom

Hi Tom,

What else do you need besides VID capture?

VID start

VID Status

Thanks

Downey

Downey,

From my previous email:

Please use CCS to extract the VCNTLID from each of the DSPs.  The VID value is readable from the VCNTLID register at 0235_0014h and extracted from bits 21:16.  Please refer to the PSC User Guide for the full register definition and the device Data Manual for the full address map.  Once you have all 4 VCNTLID values known, please post them.  Also please provide the exact part number for the devices on your board.

You state that the DSPs are sending VID code [000000].  That is not possible in a production device.  How did you determine this was the value presented?  If you captured this on a scope picture after releasing reset to the C6678, please attach scope captures showing the VID output.

I need to see scope captures of the VID value on the VCNTL lines from the DSP to the UCD controller.  They toggle shortly after reset release.  Please show all 4 on the same scope image.

Tom

Hi Tom,

Sorry for the late reply.

20210208_UCD9244_Scope.pptx

Please check the attached waveform.

The scope checks the signal as “10 0011”. but UCD9244 doesn't recognize it.

Thanks,

Downey Kim.

Hi Tom,

Sorry for the late reply.

2251.20210208_UCD9244_Scope.pptx

Please check the attached waveform.

The scope checks the signal as “10 0011”. but UCD9244 doesn't recognize it.

Thanks,

Downey Kim.

Downey,

I will look at the waveforms.  Can you also provide the VCNTLID from the register as I requested previously.

Tom

Downey,

In the waveform I see VID[2:0] (VCNTL[2:0] while VCNTL3 is low) as [010] and VID[5:3] (VCNTL[2:0] after VCNTL3 rises) as [101].  This results in the VID value of [101010] or 42d.  Does this match the VCNTLID read from the register?

You show that the UCD9244 reads a VID value of [00] for the 4th rail.  Reasonable VID values are read and displayed on the other 3 rails.  Do these values match the VCNTLID registers in those devices?

Tom

Hi Tom,

Sorry for the late update.

They added oscilloscope measured waveforms of rails 1-4.

Rail 1~3 displays the Vid value as normal like an oscilloscope. But Rail 4 doesn't work properly.

4401.20210302_UCD9244_Scope.pptx

Thanks,

Downey Kim.

Downey,

I keep asking for the VCNTL_ID read from the PSC register.  Please provide this for each of the 4 DSPs.  This cross-check is needed to determine how best to proceed.

Tom

Downey,

The 4th VID input pins are shared with the JTAG interface.  Have you verified that the JTAG port is not enabled?  Do you see any transitions on the JTAG RCK pin?

Tom

Hi Tom,

There seem to be three conditions where the JTAG interface is enabled.

Their system is designed to operate after downloading to FLASH through PMBUS.

It doesn't seem to apply to the three conditions. (For JTAG enable)

Can we check if JTAG is enabled? If yes, please tell me how.

Thanks,

Downey

Downy,

I asked you about RCK.  That should be an indication.  If RCK toggles when TCK toggles, I believe that the shared pins are functioning in JTAG mode.

Please also provide the VCNTL_ID values requested.

Tom

Downey,

What do you have connected to the ADDR[1:0] pins?

Tom