Hi we measured time of dsp_1(c66x) vs a15_0 and the same code part is running triple time slower than on 15_0,
Can you advise?
I attached the RTSC memory configuration of c66x .
and i'm using EXT_RAM for NDK in c66x like this,
Program.sectMap[".far:NDK_PACKETMEM"] = {loadSegment: "EXT_RAM", loadAlign: 128};
Program.sectMap[".far:NDK_MMBUFFER"] = {loadSegment: "EXT_RAM", loadAlign: 128};
A few questions,
1. When it tried to make split OCMC_RAMx, so one part be the code/data and 64kB to be shared memory with a15_0 and dsp, i saw a problem,
it seems when u use
var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
Cache.setMarMeta(0x405F0000, 0x10000, Cache.Mar_DISABLE); // set shared memory non-cacheable
it will turn of cache for the whole OCMC_RAMx, 1-3, but we have code there so nothing is cached and nothing works because its slow,
from DSP c66x Corepac i see that setMarMeta will set MAR64 to non-cache(PC=0) and non prefetch,
which is 16MB from 0x4000_0000 to 40FF_0000,
Can we set only part of OCMC_RAMx to be non-cache and not the whole 16MB?
2. Can we share L2SRAM of DSP c66x internal memory with a15_0 somehow?
With best regards,
Vadim.
Brad Griffis said:Do you have past experience handling cache coherence manually? I've had a lot of cases where customers were reluctant to manually manage the cache operations, but once they actually did it they realized it wasn't nearly as difficult as they expected. I still think that's the best option.
Best regards,
Brad
Hey Brad,
I can just turn of cache at arm side, and maybe in future manage "coherence". but cache and shared memory is only part of a problem, i did some measurements and even when i "mockup" the shared memory data to internal OCMC_RAMx on DSP side our code is running slow, here is the measurements:
| code performance | ||||||
| Optimization | Shared Data | Cache | Time [uSec] | Variables amount | shared bytes amount | |
| O3 | Internal (OCMC_RAMx) - mockup variables | Yes | 19.707348 | 20 | 0 bytes | |
| O3 | External (EXT_RAM) | Yes | 18.65922 | 20 | ~80 bytes | |
| O3 | External (EXT_RAM) | No | 37.671332 | 20 | ~80 bytes | |
Here us "Memory allocation of DSP"
Can you advise,
With best regards Vadim.
Yes it is expected, because i followed your advise and used L2SRAM for Shared memory between a15_0 <=> dsp_0.
Here is the new configuration,
I had no success of using the additional 32KB of memory, is it in higher address (top)? or lower address (down) this additional space? Because cache is growing from top
so i configured the cache to be 128KB and used the lower 128 KB for shared memory, and also for critical functions code section so it could run faster...
