TDA4VM: TDA4VM CPSW9G Gigabit PHY Conflict with 100M PHY, how to configure CPSW9G mac learning

Hi,

Can you provide more details

1. Which SDK are you using ?

2. What's running on A72 and R5. Which cores are receiving the data ? (If you can draw a SW block diagram with data paths, that would help)

The frame drop with 1G port is definitely not expected.

Regards

Vineet

Hi Vineet,

       Thanks for your help.

       1.We use sdk7.1.

       2.We use iperf tool to run on A72 to test Gigabit Phy, and simultaneously we use socket communication demo on A72 to test 100M phy between tda4a and mcu. But the cpsw9g drvier is running on R5.We think R5 receiving the data first then transfrom to A72.

       Could we enable the cpsw9g vlan module to fix the issue? How should we enable it?

Regards

Jason

A SW block diagram with data paths like this:

Data Path1: TDA4A CHIP A72（eth1 172.16.0.100）-->CPSW9G(TDA4A) PORT 2--->100M Phy---->MCU（ip 172.16.0.1）

Data Path2: TDA4A CHIP A72（eth1:0 172.16.200.100）-->CPSW9G(TDA4A) PORT 5--->Gigabit Phy---->PC（ip 172.16.200.190）

In Data Path2,  we use  iperf runing on TDA4A CHIP A72 （eth1:0 172.16.200.100） to send udp packets to PC（ip 172.16.200.190), then the CPSW9G(TDA4A) PORT 2 would receive the udp packets.How could we filter the packets from CPSW9G(TDA4A) PORT 5? For it would cause packets loss in Data Path1.

The frame drop with 1G port is definitely not expected.----------There's no frame drop with 1G port but 100M port I think.

Regards

Jason

Hi Vineet,

      We modify vlanMemberList of ports on CPSW9G, shown as below:

------------------------------------------------------------------------------------------------------------------

void EthHwInterVlan_setOpenPrms(Cpsw_Cfg *pCpswCfg)
{
Enet_MacPort i;

/* pCpswCfg->aleCfg.policerGlobalCfg.policingEn SHOULD BE TRUE for interVLan.
* Set to FALSE to exercise driver internal logic to auto enable policer when interVLan API
* is invoked
*/
pCpswCfg->aleCfg.policerGlobalCfg.policingEn = TRUE;
pCpswCfg->hostPortCfg.passPriorityTaggedUnchanged = TRUE;

pCpswCfg->aleCfg.modeFlags = CPSW_ALE_CFG_MODULE_EN;

pCpswCfg->aleCfg.policerGlobalCfg.redDropEn = FALSE;
pCpswCfg->aleCfg.policerGlobalCfg.yellowDropEn = FALSE;
pCpswCfg->aleCfg.policerGlobalCfg.policerNoMatchMode = CPSW_ALE_POLICER_NOMATCH_MODE_GREEN;
pCpswCfg->aleCfg.vlanCfg.aleVlanAwareMode = TRUE;
pCpswCfg->aleCfg.vlanCfg.cpswVlanAwareMode = TRUE;
pCpswCfg->aleCfg.vlanCfg.unknownVlanMemberListMask = 0;

pCpswCfg->aleCfg.nwSecCfg.hostOuiNoMatchDeny = FALSE;
pCpswCfg->aleCfg.nwSecCfg.vid0ModeEn = TRUE;
pCpswCfg->aleCfg.nwSecCfg.ipPktCfg.dfltNxtHdrWhitelistEn = TRUE;
pCpswCfg->aleCfg.nwSecCfg.ipPktCfg.ipNxtHdrWhitelistCnt = 2U;
pCpswCfg->aleCfg.nwSecCfg.ipPktCfg.ipNxtHdrWhitelist[0] = CPSW_TEST_IPV4_NXT_HDR_TCP;
pCpswCfg->aleCfg.nwSecCfg.ipPktCfg.ipNxtHdrWhitelist[1] = CPSW_TEST_IPV4_NXT_HDR_UDP;

pCpswCfg->aleCfg.portCfg[CPSW_ALE_HOST_PORT_NUM].learningCfg.noLearn = FALSE;
pCpswCfg->aleCfg.portCfg[CPSW_ALE_HOST_PORT_NUM].vlanCfg.dropUntagged = FALSE;
pCpswCfg->aleCfg.portCfg[CPSW_ALE_HOST_PORT_NUM].pvidCfg.unregMcastFloodMask = 0x0;
pCpswCfg->aleCfg.portCfg[CPSW_ALE_HOST_PORT_NUM].pvidCfg.regMcastFloodMask = CPSW_ALE_ALL_PORTS_MASK;
pCpswCfg->aleCfg.portCfg[CPSW_ALE_HOST_PORT_NUM].pvidCfg.forceUntaggedEgressMask = CPSW_ALE_ALL_PORTS_MASK;
pCpswCfg->aleCfg.portCfg[CPSW_ALE_HOST_PORT_NUM].pvidCfg.noLearnMask = 0x0;
pCpswCfg->aleCfg.portCfg[CPSW_ALE_HOST_PORT_NUM].pvidCfg.vidIngressCheck = 0x0;
pCpswCfg->aleCfg.portCfg[CPSW_ALE_HOST_PORT_NUM].pvidCfg.limitIPNxtHdr = false;
pCpswCfg->aleCfg.portCfg[CPSW_ALE_HOST_PORT_NUM].pvidCfg.disallowIPFrag = false;
pCpswCfg->aleCfg.portCfg[CPSW_ALE_HOST_PORT_NUM].pvidCfg.vlanIdInfo.tagType = ENET_VLAN_TAG_TYPE_INNER;
pCpswCfg->aleCfg.portCfg[CPSW_ALE_HOST_PORT_NUM].pvidCfg.vlanIdInfo.vlanId = CPSW_TEST_INTERVLAN_HOSTPORT_PVID;
pCpswCfg->aleCfg.portCfg[CPSW_ALE_HOST_PORT_NUM].pvidCfg.vlanMemberList = CPSW_ALE_ALL_PORTS_MASK;//0x1fb;//

for (i = ENET_MAC_PORT_FIRST; i < CPSW_ALE_NUM_MAC_PORTS; i++)
{
pCpswCfg->aleCfg.portCfg[CPSW_ALE_MACPORT_TO_ALEPORT(i)].learningCfg.noLearn = FALSE;
pCpswCfg->aleCfg.portCfg[CPSW_ALE_MACPORT_TO_ALEPORT(i)].pvidCfg.unregMcastFloodMask = 0x0;
pCpswCfg->aleCfg.portCfg[CPSW_ALE_MACPORT_TO_ALEPORT(i)].pvidCfg.regMcastFloodMask = CPSW_ALE_ALL_PORTS_MASK;
pCpswCfg->aleCfg.portCfg[CPSW_ALE_MACPORT_TO_ALEPORT(i)].pvidCfg.forceUntaggedEgressMask = CPSW_ALE_ALL_PORTS_MASK;//1<<(i+1);
pCpswCfg->aleCfg.portCfg[CPSW_ALE_MACPORT_TO_ALEPORT(i)].pvidCfg.noLearnMask = 0x0;
pCpswCfg->aleCfg.portCfg[CPSW_ALE_MACPORT_TO_ALEPORT(i)].pvidCfg.vidIngressCheck = 0x0;
pCpswCfg->aleCfg.portCfg[CPSW_ALE_MACPORT_TO_ALEPORT(i)].pvidCfg.limitIPNxtHdr = false;
pCpswCfg->aleCfg.portCfg[CPSW_ALE_MACPORT_TO_ALEPORT(i)].pvidCfg.disallowIPFrag = false;
pCpswCfg->aleCfg.portCfg[CPSW_ALE_MACPORT_TO_ALEPORT(i)].pvidCfg.vlanIdInfo.tagType = ENET_VLAN_TAG_TYPE_INNER;
pCpswCfg->aleCfg.portCfg[CPSW_ALE_MACPORT_TO_ALEPORT(i)].pvidCfg.vlanIdInfo.vlanId = CPSW_TEST_INTERVLAN_MACPORT_PVID_BASE + ENET_MACPORT_NORM(i);
pCpswCfg->aleCfg.portCfg[CPSW_ALE_MACPORT_TO_ALEPORT(i)].pvidCfg.vlanMemberList = 0x1;//CPSW_ALE_ALL_PORTS_MASK;
}

pCpswCfg->hostPortCfg.vlanCfg.portPri = 7;
pCpswCfg->hostPortCfg.vlanCfg.portCfi = 0;
pCpswCfg->hostPortCfg.vlanCfg.portVID = CPSW_TEST_INTERVLAN_HOSTPORT_PVID;
pCpswCfg->vlanCfg.vlanAware = TRUE;
}

------------------------------------------------------------------------------------------------------------------

so CPSW9G(TDA4A) PORT 2 and PORT 5 can only communicate with  CPSW9G(TDA4A) host port, but when we use iperf to send udp packets from CPSW9G(TDA4A) host port to PORT 5, PORT 2 still could receive the packets too.We need to send the packets directly to PORT 5, meanwhile host port can communicate with PORT 2 normally.

Regards,

Jason

Hi Jason,

Sorry, re-opening this thread after some time.

Is this issue still open ?

Regards

Vineet

Hi Vineet,

       The issue is still open, we finally use tcp protocol to communicate with PORT5.

Regards,

Jason

Hi,

Sorry for the delay. I am working on a VLAN/ALE user guide for TDA4 which will cover this topic.

Regards

Vineet

Hi Vineet,

     Thanks very much. If possible, can you send me a related user guide, my email is huangjiasheng@yihang.ai 

Regards,

Jason

Hi,

Please take a look at this FAQ

Regards

Vineet