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Part Number: AM62X-PET-CALC
Hi TI
When i finish the PINMUX config and power domain config, there is confict message show as below，Can i suppress these two warning ?
As the MCU GPIO is 3v3 level ,so i connect the VDDSHV_MCU to 3v3 domain.
BR…
Part Number: AM6442
Problem Description
The MCU+ SDK comes with a GPIO_INPUT_INTERRUPT example for R5FSS0-0. This example configures a GPIO pin to generate an interrupt and then registers an interrupt handler to service the GPIO interrupt. This example…
Part Number: SK-AM62
What is GPIO?
The General-Purpose Input/output (GPIO) peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs.
GPIO can be used in three modes:
*Input
*Output
*Interrupt
…
Part Number: TMS320C6678 Other Parts Discussed in Thread: CCSTUDIO How to set Static and DHCP IP configuration using PDK in C667x and C665x family Processors ?
Part Number: PROCESSOR-SDK-TDAX Other Parts Discussed in Thread: TDA4VM
VHWA has totally 6 drivers in the PDK and each driver requires many DMA channels to do transfers. In addition to one main ring, each channel requires two additional rings, one for…
I am not using one of the cores on my TI processor. How do I disable that core, so that I can free up more memory, peripherals, etc for my other cores?
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This FAQ will use AM64x as an example, but the same concepts apply for AM62x.
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NOTE: This…
Part Number: AM3354
Hi there,
I am using the AM3354 CPU.
For cybersecurity, I want the JTAG port to be protected, to avoid others read out our binary code. The CPU can only be full ereased after this protection.
Please tell me how to achieve this…
Part Number: TDA4VM When testing SDL (Software Diagnostics Library) package on the TDA4VM, seeing LBIST HW POST Timeout logs as below.
BIST Example Application
Starting LBIST test on HWPOST - DMSC, index 0... HW POST MCU Status : SDL_LBIST_POST_TIMEOUT…
Part Number: AM6442 Other Parts Discussed in Thread: SYSCONFIG
UPDATE: This FAQ has been replaced by the Multicore academy module, section "Application Development on Remote cores". Please refer to the associated processor academy. This FAQ will not…
