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RTOS/AM5726: MMU setup

Part Number: AM5726
Other Parts Discussed in Thread: SYSBIOS

Tool/software: TI-RTOS

I'm trying to work through setting up the MMU for an RTOS application on the Cortex-A15.  I have read the documentation here:

Though we have tried several iterations of configuring a page for the GPMC address space, we cannot get a level 2 entry to work.  We can only get a level 1 entry to work, and I have no good understanding of what I'm doing with these API's.  Is there additional documentation available on this MMU device driver.  Perhaps a more in depth tutorial?

Thanks,

Stuart

  • The RTOS team have been notified. They will respond here.
  • Hi,

    Can you check if this helps? e2e.ti.com/.../579072. It has how to setup Level 1/2 MMU on GPMC interface, through SYSBIOS configuration.

    Regards, Eric
  • Eric,

    I read through the thread, but unfortunately it leaves me with more questions than answers.  Please see the following configuration file that we modified from the I2C example to add two memory regions to the MMU mapping.

    4466.i2c_arm_evmAM572x_master.cfg

    This did not seem to work, and resulted in an exception right away when accessing the GPMC address space.

    Next we added the following, which still did not work:

    Finally, we added the following configuration (at runtime):

    void mmu_mapping(void)
    {
        Mmu_DescriptorAttrs peripheralAttrs;
        Mmu_initDescAttrs(&peripheralAttrs);
        peripheralAttrs.type = Mmu_DescriptorType_BLOCK;
        peripheralAttrs.noExecute = true;
        peripheralAttrs.accPerm = 0;
        peripheralAttrs.attrIndx = 1;
        Mmu_setFirstLevelDesc((Ptr)0x00000000, (UInt64)0x00000000, &peripheralAttrs);
    }
    

    This last configuration worked, but we have no idea why.  The only difference of significance that we can gather is that it is a first level descriptor rather than a second level descriptor.  I think part of the confusion may be that we have no idea what the different attribute parameters mean, as their documentation is non-descript.  Especially accPerm and attrIndx, but I would say the same about all of the members of the Mmu_DesciprtorAttrs structure.

    Thanks,

    Stuart

  • Stuart Baker said:
    This did not seem to work, and resulted in an exception right away when accessing the GPMC address space.

    What is the size of the GPMC address region, and at what address did the exception occur?

    As per the module ti.sysbios.family.arm.a15.Mmu documentation each entry in the level1 table gives the base address and defines the attributes of a memory area of size 1GB, whereas each entry in the level2 table gives the base address and defines the attributes of a memory area of size 2MB.

    Therefore, if the GPMC address region is more than 2MB multiple Mmu.setSecondLevelDescMeta() calls will be required to map the entire GPMC address region. The referenced documentation shows Mmu.setSecondLevelDescMeta being called in a loop in the .cfg script where the address is incremented 2MB at a time to map an entire region.

    Stuart Baker said:
    Especially accPerm and attrIndx, but I would say the same about all of the members of the Mmu_DesciprtorAttrs structure.

    The documentation for Mmu_setMAIR explains the meaning of the attrIndx, where with the SYS/BIOS defaults an attrIndx of 1 is "mark memory region as strongly ordered and non-cacheable" which is suitable for peripherals.

    See the ARM v7AR Architecture Reference Manual, which is referenced from the SYS/BIOS documentation for the ti.sysbios.family.arm.a15.Mmu module.

    [You need to register with ARM to get the ARM v7AR Architecture Reference Manual]