RTOS/PROCESSOR-SDK-AM335X: Timers crash on Initialization

Hello Sahin,

I do use "pdk_am335x_1_0_8" and "processor_sdk_rtos_am335x_4_01_00_06" with a beaglebone black. I tried to use a timer with the example project "MCSPI_SlaveMode_SlaveExample_bbbAM335x_armExampleProject" or with a newly created sys bios project. In both cases the software crashes at that function. As I said, before I updated everything worked find with the timers.

Source extract:

uint32_t ulusCounter = 0;

void usTimer()
{
    /*120: 5us*/
    ulusCounter+=5;
}

void StartMsTimerTask()
{
    Timer_Params timer_params;

         Error_Block eb_timer;

         Error_init( &eb_timer );

         Timer_Params_init( &timer_params );
/*120: 5us*/
         timer_params.period = 2000;

         timer_params.periodType = Timer_PeriodType_COUNTS;

         timer_params.startMode = Timer_StartMode_AUTO;

         timer_params.runMode = Timer_RunMode_CONTINUOUS;

         Timer_create(5, (Timer_FuncPtr)usTimer, &timer_params, &eb_timer );

         return 0;
}
/*
 *  ======== taskFxn ========
 */
Void taskFxn(UArg a0, UArg a1)
{
    System_printf("enter taskFxn()\n");
    StartMsTimerTask();
    Task_sleep(10);

    System_printf("exit taskFxn()\n");

    System_flush(); /* force SysMin output to console */
}

/*
 *  ======== main ========
 */
Int main()
{
    Task_Handle task;
    Error_Block eb;

    System_printf("enter main()\n");

    Error_init(&eb);
    task = Task_create(taskFxn, NULL, &eb);
    if (task == NULL) {
        System_printf("Task_create() failed!\n");
        BIOS_exit(0);
    }

    BIOS_start();    /* does not return */
    return(0);
}

UPDATE 22.01.2018: When adding the following line to the cfg file the system instantly crashes when I try to start debugging. Any Ideas?

Added line: "ti_sysbios_timers_dmtimer_Timer.intFreq.lo = 12000;"

I didn't change anything to update to current System. My Setup is now as follows.

Setup:

GCC: gcc-arm-none-eabi-6-2017-q1-update
BIOS: bios_6_52_00_12
NDK: ndk_2_26_00_08
PDK: pdk_am335x_1_0_9
PSDK: processor_sdk_rtos_am335x_4_02_00_09
XDC: xdctools_3_50_03_33_core
Sitara: Sitara_1_02_00_00
EDMA: edma3_lld_2_12_05_30B

UPDATE 22.01.2018: When looking into DMTIMER registers at startup I could see the only DMTIMER0 and DMTIMER2 are readable. Do I need to configure them somewhere in startup file before I can use them?

UPDATE 22.01.2018: Problem is solved. You need to update the GEL file or activate the DMTIMERS in sourcecode. GEL File Activation Example (Link: http://e2e.ti.com/support/embedded/bios/f/355/p/270589/946269.aspx#946269:

#define CM_PER            (0x44e00000)
#define CM_DPLL            (0x44e00500)

#define CM_PER_TIMER2_CLKCTRL    (CM_PER + 0x80)
#define CM_PER_TIMER3_CLKCTRL    (CM_PER + 0x84)
#define CM_PER_TIMER4_CLKCTRL    (CM_PER + 0x88)
#define CM_PER_TIMER5_CLKCTRL    (CM_PER + 0xEC)
#define CM_PER_TIMER6_CLKCTRL    (CM_PER + 0xF0)
#define CM_PER_TIMER7_CLKCTRL    (CM_PER + 0x7C)

#define CLKSEL_TIMER2_CLK    (CM_DPLL + 0x04)
#define CLKSEL_TIMER3_CLK    (CM_DPLL + 0x08)
#define CLKSEL_TIMER4_CLK    (CM_DPLL + 0x0C)
#define CLKSEL_TIMER5_CLK    (CM_DPLL + 0x14)
#define CLKSEL_TIMER6_CLK    (CM_DPLL + 0x18)
#define CLKSEL_TIMER7_CLK    (CM_DPLL + 0x00)

hotmenu EnableTimers_32KHz()
{
    WR_MEM_32(CM_PER_TIMER2_CLKCTRL, 0x2);
    WR_MEM_32(CLKSEL_TIMER2_CLK, 0x2);

    WR_MEM_32(CM_PER_TIMER3_CLKCTRL, 0x2);
    WR_MEM_32(CLKSEL_TIMER3_CLK, 0x2);

    WR_MEM_32(CM_PER_TIMER4_CLKCTRL, 0x2);
    WR_MEM_32(CLKSEL_TIMER4_CLK, 0x2);

    WR_MEM_32(CM_PER_TIMER5_CLKCTRL, 0x2);
    WR_MEM_32(CLKSEL_TIMER5_CLK, 0x2);

    WR_MEM_32(CM_PER_TIMER6_CLKCTRL, 0x2);
    WR_MEM_32(CLKSEL_TIMER6_CLK, 0x2);

    WR_MEM_32(CM_PER_TIMER7_CLKCTRL, 0x2);
    WR_MEM_32(CLKSEL_TIMER7_CLK, 0x2);

        GEL_TextOut("Timers 2-7 enabled for 32KHz.\n");
}

OnTargetConnect()
{
    GEL_MapOff();
    GEL_MapReset();
    GEL_MapAddStr(0x00020000, 0, 0x0000C000, "R", 0);    // Boot ROM
    GEL_MapAddStr(0x08000000, 0, 0x01000000, "R|W", 0);  // 16MB GPMC External/NOR (on GP Daughtercard)
    GEL_MapAddStr(0x40020000, 0, 0x0000C000, "R", 0);    // Boot ROM (also at 0x20000)
    GEL_MapAddStr(0x402F0400, 0, 0x0000FC00, "R|W", 0);  // SRAM Internal
    GEL_MapAddStr(0x40300000, 0, 0x00010000, "R|W", 0);  // OCMC-RAM
    GEL_MapAddStr(0x44000000, 0, 0x00400000, "R|W", 0);  // L3F CFG Regs
    GEL_MapAddStr(0x44800000, 0, 0x00400000, "R|W", 0);  // L3S CFG Regs
    GEL_MapAddStr(0x44C00000, 0, 0x00400000, "R|W", 0);  // L4_WKUP
    GEL_MapAddStr(0x46000000, 0, 0x00400000, "R|W", 0);  // McASP0 Data
    GEL_MapAddStr(0x46400000, 0, 0x00400000, "R|W", 0);  // McASP1 Data
    GEL_MapAddStr(0x47400000, 0, 0x00005000, "R|W", 0);  // USB0/1
    GEL_MapAddStr(0x47810000, 0, 0x00010000, "R|W", 0);  // MMCHS2
    GEL_MapAddStr(0x48000000, 0, 0x01000000, "R|W", 0);  // L4 PER
    GEL_MapAddStr(0x49000000, 0, 0x00B00000, "R|W", 0);  // EDMA
    GEL_MapAddStr(0x4A000000, 0, 0x01000000, "R|W", 0);  // L4_FAST
    GEL_MapAddStr(0x4C000000, 0, 0x01000000, "R|W", 0);  // EMIF
    GEL_MapAddStr(0x50000000, 0, 0x01000000, "R|W", 0);  // GPMC Regs
    GEL_MapAddStr(0x56000000, 0, 0x01000000, "R|W", 0);  // SGX530
    GEL_MapAddStr(0x80000000, 0, 0x20000000, "R|W", 0);  // 512MB DDR3 external memory
    GEL_MapOn();
    GEL_AdvancedReset("System Reset"); // Reset the board to avoid conflicts with program running from NOR/SPI/SD
    GEL_Halt();                        // System Reset leaves the core running. Needs to halt it so memory can be accessed
    Disable_Watchdog();
    AM335x_BeagleBlack_Initialization();
    EnableTimers_32KHz();
}

Values can be as follows (ref. Am335x_referenceManual):

CLKSEL_TIMERx_CLK:

Selects the Mux select line for TIMERx clock [warm reset insensitive]
0x0 = SEL1 : Select TCLKIN clock (external timer clock soure)
0x1 = SEL2 : Select CLK_M_OSC clock (System clock)
0x2 = SEL3 : Select CLK_32KHZ clock (pll 32.768 Khz clock)
0x3 = SEL4 : Reserved

CM_PER_TIMERx_CLKCTRL:

Control the way mandatory clocks are managed.
0x0 = DISABLED : Module is disable by SW. Any OCP access to
module results in an error, except if resulting from a module wakeup
(asynchronous wakeup).
0x1 = RESERVED_1 : Reserved
0x2 = ENABLE : Module is explicitly enabled. Interface clock (if not
used for functions) may be gated according to the clock domain
state. Functional clocks are guarantied to stay present. As long as in
this configuration, power domain sleep transition cannot happen.
0x3 = RESERVED : Reserved

UPDATE: When not using SYS BIOS the timers can be activated as follows (extract from starterware/platform/evmAM335x/dmtimer.c)

Code extract:

}