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Original question:

66AK2H06: SerDes PLL reference clock input

66AK2H06: USB Clock termination

Koichiro Tashiro
Mastermind 21750 points
Part Number: 66AK2H06
Other Parts Discussed in Thread: 66AK2H14

Hi,

This is additional question for the original post.

Customer observed overshoot/undershoot on USBCLK.
According to the original thread, USBCLK are not terminated until the software is loaded and the SERDES interface is initialized.
Customer loaded and initialized the USB module and now compliance test was passed.
But USBCLK waveform still shows overshoot/undershoot.
If customer added 100-ohm termination on USBCLK, the overshoot/undershoot disappeared.
Please see attached xls.
USB_clock.xlsx
Is this true the SERDES will apply 100-ohm termination and no termination is needed externally?
Or customer needs to setup specific register or bit to enable the internal termination?

Thanks and regards,
Koichiro Tashiro

  • 0
    TI__Mastermind 46460 points

    Tashiro-san,

    As you stated, the SERDES software enables the terminations when the driver is loaded.  You stated that the USB compliance test passed once the driver was loaded.  You attached two scope captures.  Were these taken while the driver was loaded and active?  What did the input look like prior to the driver being loaded?

    An external termination is not recommended.  What is the driving source for this clock?  Is it LVDS or LVPECL complaint with a source impedance of 100 ohms differential?

    Tom

  • 0 in reply to Tom Johnson 16214
    TI__Mastermind 46460 points

    Tashiro-san,

    Are you able to get answers to my questions?

    Tom

  • 0 in reply to Tom Johnson 16214
    TI__Mastermind 46460 points

    Tashiro-san,

    Since there have been no responses, I will close this thread.  If you want to re-open it, simply post to this thread.  If it becomes locked, you can open a new thread and link them together.

    Tom

  • 0 in reply to Tom Johnson 16214
    TI__Mastermind 21750 points

    Hi Tom,


    Sorry for the delay.
    We were in holidays last week in Japan.
    Please see answers to your questions.

    >Were these taken while the driver was loaded and active?

    The upper waveform is the one while the driver was loaded and active.
    The device(66AK2H) is connected to PC via USB and recognized properly in Windows.

    >What did the input look like prior to the driver being loaded?

    Customer compares waveforms before and after the driver being loaded, but they are the same.
    I am afraid some settings are missed to enable SERDES termination in customer’s code.
    Could you point me which register and bit enable SERDES termination?

    > What is the driving source for this clock? Is it LVDS or LVPECL complaint with a source impedance of 100 ohms differential?

    The source side of the clock is below;
    https://www.idt.com/jp/ja/document/dst/idt8slvd1208-33i-datasheet
    This source is used for SYSCLK, ARMCLK, DDRACLK and PCIECLK as well.
    PCIECLK gets cleaner after PCIE initialization is done. Only USBCLK shows overshoot/undershoot.

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Mastermind 46460 points

    Tashiro-san,

    >>Were these taken while the driver was loaded and active?

    The upper waveform is the one while the driver was loaded and active. The device (66AK2H) is connected to PC via USB and recognized properly in Windows.

     

    TI: I am confused. You previously stated that the USB compliance test passed once the configuration software was executed. Here you state that the upper waveform capture showing the reflections was captured the driver was loaded and active. Are you saying that it is functionally compliant with the distorted clock but your concern is simply with the cleanliness of the clock signal?

     

    >> What is the driving source for this clock? Is it LVDS or LVPECL complaint with a source impedance of 100 ohms differential?

    The source side of the clock is below;

    www.idt.com/.../idt8slvd1208-33i-datasheet

    This source is used for SYSCLK, ARMCLK, DDRACLK and PCIECLK as well.

    PCIECLK gets cleaner after PCIE initialization is done. Only USBCLK shows overshoot/undershoot.

     

    TI: I need more than a datasheet. I need to know the components and circuit connections between this LVDS clock fan-out buffer and the USBCLK input.

     

    Tom

  • 0 in reply to Tom Johnson 16214
    TI__Mastermind 21750 points

    Hi Tom,

    For the 1st point;
    Yes, the USB is working properly and compliance test is passing with the dirty clock (upper waveform).
    Customer’s concern is the waveform does not change regardless software loaded or not.
    He wonders some settings are missed in their code.

    For the 2nd point;
    I will send you a part of customer’s schematic offline.

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Mastermind 46460 points

     Tashiro-san,

    I did some more research. I found that the USB IP block is different that the other SERDES IP blocks on this device. As you can see, it is not mentioned in the KeyStone II Architecture Serializer/Deserializer (SerDes) User's Guide (SPRUHO3A). The SERDES reference clocks are the ones that require the software driver to be executed before the reference clock is properly terminated. The USB-SS interface is described in the KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) User's Guide (SPRUHJ7A).  However, I cannot find any reference to software control for the termination for the reference clock input.  I do know that the USB-SS port on the 66AK2H14 device has passed our compliance tests.  I expect that we passed our tests with the same clock that the customer is seeing.  Since it passes compliance without the external termination resistor and since the reference clock signal still meets the LVDS signal definition when the external resistor is added, the customer can choose to either add the external termination or leave it off.

    Tom

  • 0 in reply to Tom Johnson 16214
    TI__Mastermind 21750 points

    Hi Tom,

    I see. I understood there is no internal termination for USBCLK SerDes.
    It is very difficult to find this information from current documents.
    Customer wants TI to add this information somewhere.
    Could you update datasheet or user’s guide?

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Mastermind 46460 points

    Tashiro-san,

    We will submit a request to have this better explained.

    Tom