Other Parts Discussed in Thread: LMK04828, , LMX1204
Tool/software:
I am trying to figure out the best way to provide the SYSREF clocking signal to the AFE7950. The constraints on common mode voltage and input swing make this unintuitive.
The AFE7950 appears to divide down an LVPECL output from the LMK04828 but simulation shows that this would not meet the input requirements. This analysis is captured here:
https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1419139/lmk04828-clk-output-divider
Can you provide any insight into what the configuration of the AFE7950EVM is intended to be or what differential standard and termination the part is expecting?