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AFE7950: SYSREF Input Format and Termination

Part Number: AFE7950
Other Parts Discussed in Thread: LMK04828, , LMX1204

Tool/software:

I am trying to figure out the best way to provide the SYSREF clocking signal to the AFE7950. The constraints on common mode voltage and input swing make this unintuitive.

The AFE7950 appears to divide down an LVPECL output from the LMK04828 but simulation shows that this would not meet the input requirements. This analysis is captured here:
https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1419139/lmk04828-clk-output-divider

Can you provide any insight into what the configuration of the AFE7950EVM is intended to be or what differential standard and termination the part is expecting?

  • Hi Erik,

    Connecting the SYSREF like in the AFE7950EVM and using the HSDS 8mA output mode of the LMK04828 results on a proper SYSREF common and Vppdif levels.

    As an example, we probed the SYSREF on the EVM and got the following results.

    • Vcm = 610 mV
    • Vpp_dif = 750 mV

    Let me know if this answers your query.

    Best,

    Camilo

  • Hello Camilo,

    Thank you for your response. I had assumed the LMK04828 output was not HSDS because the datasheet states that it should be AC coupled.

    It sounds like this is not the case?

    I am unfamiliar with the drive circuit for the HSDS output, but the LMK04828 datasheet puts the nominal Vcm at 1.62V. If the resistor network on the AFE7950 divided that output ideally then the resulting common mode voltage would be (slightly) above the 0.8V maximum.

    Do you know why the measured common mode voltage is below this value? Is the 0.8V maximum a hard limit?

    Finally, is there another output format and termination scheme or an independent HSDS transceiver IC that could be used to interface with the AFE7950? We are using a discrete clocking source in our design and not the LMK04828.

    Thanks again for your help,

    Erik

  • Hi Erik,

    You would need to meet the datasheet SYSREF Vcm specs in order to guarantee the datasheet specs. So we would recommend staying between the VCOM_SRMIN and the VCOM_SRMAX. 

    In regards to the divider, you must also account for the termination inside the device.

    If you do not have an output format in mind, you have a good number of options such as:

    • Using a device with an output format that has a higher VCM and Vdiff_pp which you could then adjust by using a resistor divider.
    • If you do not need to use single shot SYSREF to synchronize multiple AFEs, you could AC couple SYSREF to the AFE.
    • Using a clocking buffer such as the LMX1204.

    If you are still not sure, we can forward this thread to our clocking team so that they can help you. Let us know how you would like to proceed.

    Best,

    Camilo