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Tool/software:
We are currently testing a JESD204B project using the ZCU106 Evaluation FPGA Board in conjunction with the AFE7950 EVM. On the FPGA side, the LMFSH value is set to 24410, and the LMFSH value on the AFE side is also 24410, with only one instance in use.We are using the DC135-AFE7950EVM board, but we have been unable to locate its schematic. As an alternative, we have referenced the schematic for the DC150A-AFE7950EVM board. Could you kindly confirm if this approach is acceptable? If not, could you please guide me to where I can find the required schematic?
The following steps were performed:
Please refer to the attached configuration script for additional details. after running the below script we are facing below errors in the Latte log.
In the design, we are configuring some of the internal registers of the JESD204C on both the RX core and TX core sides using the AXI protocol. We are sending counter data to the ADC while simultaneously collecting data from the DAC.
Upon receiving the GT_POWERGOOD signal, we assert the reset and, after a brief period, de-assert the reset. This reset process occurs simultaneously with the configuration of the AFE board.
Currently, eventhough we got errors in log file,we are observing that the TX_RESET_DONE and RX_RESET_DONE signals are being asserted as expected; however, the SYNC signal is not coming from the DAC_JESD_rx or the RX_FPGA JESD. Interestingly, if I manually assert the reset again after configuring the AFE, the TX_SYNC signal is generated, but the RX_SYNC signal is still absent.
For further reference, please find the attached screenshot detailing the issue. If the RX_SYNC signal is not being generated, the ADC JESD_TX should be sending comma characters. However, I am observing random data instead.
In a separate scenario, I reset the system and started configuring the AFE board, but I de-asserted the reset before the AFE configuration was completed.This time is didn't get any errors in latte log,And I was able to observe both RX_SYNC and TX_SYNC signals; however, random data is being received from the ADC on the RX side, which does not appear to be correct. I have attached a screenshot for reference.
Could you please help identify where I may have gone wrong and confirm if the reset procedure I am using is correct? And Could you please help identify the cause of this behavior or confirm if there might be an issue with my configuration? Additionally, I attempted to send constant data using the Latte GUI, but this did not work either. Could you kindly explain how to proceed further?"
