AFE7950EVM: AFE7950 qpll0 is not getting locked when configured through AFE79xx-Latte GUI

Hi,

Yes, if the LED "PLL2 Locked" is on then indicates that the LMKs PLL2 has locked. Have you tried probing the FPGA clock at the LMK output to verify you see the right frequency? 

Regards,

David Chaparro 

Hi David,
Thank you for your response.
We have not found any direct probe point available to verify the LMK output clock. Could you kindly guide us regarding where on the board we can find the probe and any possible label it may have so that we can verify the frequency. Looking forward to your guidance.

Hi David,

Thank you for your response. We have probed the 122.88 MHz crystal oscillator at R309 and the LMK clock near C275 (1474.56 MHz)  and are getting the correct LMK clock frequency albeit with very low power of -45.16dBm as shown below. Could you kindly tell us if this is the expected behaviour and if not, what could be causing such attenuation.

We have also observed variation in the behaviour of the qpll locking with each power cycle. There are cases where the qpll locks immediately, but in the next power cycle it doesn't lock or it takes too long to lock sometimes even fluctuating between a locked and unlocked state.

This is the case where the qpll locked for us and the corresponding error in the LATTE console:

This is the case where the qpll locked but then unlocked again and the corresponding errors in the LATTE GUI upon running the AFEConfig.py script:

The LMK PLL locks and the clock comes correctly irrespective of whether the qpll in the chipscope locks or not. One of our concerns is that since the qpll not locking is resulting in the SERDES lane errors in due to the quads in the GT not receiving the correct clock but we are unsure of how to check this on our FPGA. Could you kindly explain us the logic behind when the VIO signal(qpll0) is programmed to lock and change its value?

Thank you for your assistance.

Hi, David we are sharing the JESD params header code used in the RTL as well as the LMKConfig script:

// The following parameter defines if the 
// IP is in 8b/10b mode or 64b/66b mode
// Leave the second line commented if it is
// in 64b/66b, else uncomment it to enable 8b/10b
`undef IP_8B10B
`undef IP_64B66B
//`define IP_8B10B
`define IP_64B66B

`undef IP_TYPE
`define IP_TYPE "RXTX"

`undef ADC_RESOLUTION
`define ADC_RESOLUTION 16

`undef DAC_RESOLUTION
`define DAC_RESOLUTION 16
/////////////////////////////////////////////////
// The following parameters configure the JESD IP
// to interact with the transceiver created using
// the Vivado Transceiver wizard.
// Please ensure that the settings/parameters match
// that of the transceiver
/////////////////////////////////////////////////

// Set the number of lanes in the link
// This is equal to the number of lanes/channels
// in the transceiver IP
`undef NUMBER_OF_RX_LANES
`undef NUMBER_OF_TX_LANES

`define NUMBER_OF_RX_LANES 8
`define NUMBER_OF_TX_LANES 8

// Set the number of quads used in the transceiver
// IP. This is based on the transceiver Quad/Lane
// mapping. In this case, the 8 lanes are spread over
// 2 Quads
`undef NUMBER_OF_QUADS
`define NUMBER_OF_QUADS 2

// Select the type of Transceiver used in the IP
// Options are: GTH, GTP, GTX and GTY. Refer to
// the IP user guide for more details
// GTH :Ultrascale GTH
// GTHP :Ultrascale+ GTH
// GTY :Ultrascale GTY
// GTYP :Ultrascale+ GTY
// GTX : GTX in Zynq/Virtex/Kintex 7000 series
// GTP : GTP in Artix 7000 series
`undef MGT_TYPE
`define MGT_TYPE "GTHP"

// Set the number of Reference Clock
// Buffers used by the Transceiver
// In most cases, there is one clock per
// link, and the clock is internally routed
// to the individual Quad/Channel clocking logic
`undef NUMBER_OF_REFCLK_BUFFERS
`define NUMBER_OF_REFCLK_BUFFERS 1

// The following parameter controls the mapping
// of the ADC lanes to the transceiver lanes
// This helps account for any lane mapping mismatches
// on account of the board routing
// This parameter is from the perspective of the ADC
// and is ordered as {LANE_N,...,LANE2,LANE1,LANE0}
// For example a value of {3,1,0,2} will mean the 
// following:
//   1> Lane 0 of ADC is mapped to Lane 2 of the transceiver
//   2> Lane 1 of ADC is mapped to Lane 0 of the transceiver
//   3> Lane 2 of ADC is mapped to Lane 1 of the transceiver
//   4> Lane 3 of ADC is mapped to Lane 3 of the transceiver
// NOTE: Ensure that the parameter below has as many bits
// as the number of lanes on the transceiver
`undef LANE_ADC_TO_GT_MAP
`define LANE_ADC_TO_GT_MAP {5,4,6,7,3,0,2,1}//
//`define LANE_ADC_TO_GT_MAP  {3'd6, 3'd7, 3'd5, 3'd1, 3'd4, 3'd3, 3'd0, 3'd2}//

`undef LANE_DAC_TO_GT_MAP
`define LANE_DAC_TO_GT_MAP {4,5,6,7,3,0,2,1}//
//`define LANE_DAC_TO_GT_MAP {3'd4, 3'd5, 3'd7, 3'd6, 3'd2, 3'd3, 3'd0, 3'd1} //
// The following parameter controls the polarity
// of the transceiver lanes. If the P and N differential
// pins are inverted between the transmitter and receiver,
// set the corresponding bit to '1'. If there is no inversion
// set the corresponding bit to 0.
// This parameter is from the perspective of the ADC
// and is ordered as {LANE_N,...,LANE2,LANE1,LANE0}
// NOTE: Ensure that the parameter below has as many bits
// as the number of lanes on the transceiver
`undef RX_LANE_POLARITY
`define RX_LANE_POLARITY 8'b00110011
//`define RX_LANE_POLARITY 8'b00100101


`undef TX_LANE_POLARITY
`define TX_LANE_POLARITY 8'b00001111
//`define TX_LANE_POLARITY 8'b01100100

// Set the width of the final lane data bus exported
// by each lane of the Rx IP.
`undef RX_LANE_DATA_WIDTH
`define RX_LANE_DATA_WIDTH 64

// Set the width of the final lane data bus exported
// by each lane of the Tx IP.
`undef TX_LANE_DATA_WIDTH
`define TX_LANE_DATA_WIDTH 64

// End of parameters related to the transceiver
//////////////////////////////////////////////

//////////////////////////////////////////////
// The rest of the parameters configure the IP
// for the correct operation of the 8b/10b data
// link protocol
// PLEASE NOTE: The parameters MUST be set based
// on those of the transmitting device, without
// which the link will not work or may display
// intermittent failures
//////////////////////////////////////////////

///////////////////////////////////////////////////////////
// Parameters related to 8b/10b encoding
// These parameters are ignored if 8b/10b is chosen

// The following parameter sets the value
// of the F (octets per frame) parameter of
// the device. Refer to the device datasheet
// for the values allowed. 
`undef RX_F_VAL
`define RX_F_VAL 2

`undef TX_F_VAL
`define TX_F_VAL 2

// The following parameter sets the value
// of the K (frames per multiframe) parameter of
// the device. Refer to the device datasheet
// for the values allowed. 
`undef RX_K_VAL
`define RX_K_VAL 32

`undef TX_K_VAL
`define TX_K_VAL 32

// End of parameters related to 8b/10b 
///////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////
// Parameter related to 64b/66b Encoding
// The following parameter sets the value
// of the E (multiblocks per extended multiblock) parameter of
// the device. Refer to the device datasheet
// for the values allowed. 
// This parameter is ignored if 8b/10b is chosen
`undef RX_E_VAL
`define RX_E_VAL 4

`undef TX_E_VAL
`define TX_E_VAL 1
///////////////////////////////////////////////////////////

`undef RBD_COUNT_WIDTH
`define RBD_COUNT_WIDTH 10

// End of parameters related to deterministic latency
///////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////
// The following parameters are for the RX and TX BUFFERs
///////////////////////////////////////////////////////////
`undef RX_BUFFER
`define RX_BUFFER "NORM"

`undef BUFFER_RATIO
`define BUFFER_RATIO 1

`undef TX_BUFFER
`define TX_BUFFER "NORM"

///////////////////////////////////////////////////////////
// Define if the Clock Chip is emulated on the FPGA
///////////////////////////////////////////////////////////
//`undef SYSREF_GEN
//`define SYSREF_GEN

//`undef SYSREF_TARGET_COUNT
//`define SYSREF_TARGET_COUNT 96

'''
Validation : AFE79xx Library Version 
v1.67, v1.74
Case RX TX FB CLK Notes
---- ----------------- ----------------- ----------------- ----------- ------------
1 245.76Msps, 24410 491.52Msps, 44210 491.52Msps, 22210 FADC=2949.12M DAC in interleaved mode
SerDes=9830.4Mbps SerDes=9830.4Mbps SerDes=9830.4Mbps FDAC=8847.36M
PLL0, NCO=3500M PLL0, NCO=3500M NCO=3500M REF=491.52M
2 245.76Msps, 24410 491.52Msps, 44210 491.52Msps, 22210 FADC=2949.12M DAC in straight mode
SerDes=9830.4Mbps SerDes=9830.4Mbps SerDes=9830.4Mbps FDAC=8847.36M
PLL0, NCO=3500M PLL0, NCO=3500M NCO=3500M REF=491.52M
'''
setupParams.skipFpga = 1
sysParams = AFE.systemParams
setupParams.fpgaRefClk = 184.32
AFE.systemStatus.loadTrims = 1

sysParams.fbEnable = [False]*2
sysParams.FRef = 491.52
sysParams.FadcRx = 2949.12
sysParams.FadcFb = 2949.12
sysParams.Fdac = 2949.12*3
# sysParams.externalClockRx = False
# sysParams.externalClockTx = False

sysParams.enableDacInterleavedMode = False #DAC interleave mode to save power consumption. Fs/2 - Fin spur occurs

sysParams.modeTdd = 0 
# 0- Single TDD Pin for all Channels
# 1- Separate Control for 2T/2R/1F
# 2- Separate Control for 1T/1R/1F 

sysParams.topLevelSystemMode = 'StaticTDDMode'
sysParams.RRFMode = 0 #4T4R2F FDD mode
sysParams.jesdSystemMode = [3,3]
#SystemMode 0: 2R1F-FDD ; rx1-rx2-fb-fb
#SystemMode 1: 1R1F-FDD ; rx1-rx1-fb-fb
#SystemMode 2: 2R-FDD ; rx1-rx1-rx2-rx2
#SystemMode 3: 1R ; rx1-rx1-rx1-rx1
#SystemMode 4: 1F ; fb-fb-fb-fb
#SystemMode 5: 1R1F-TDD ; rx1/fb-rx1/fb-rx1/fb-rx1/fb
#SystemMode 8: 1R1F-TDD 1R-FDD (FB-2Lanes)(RX1 RX2 interchanged) ; rx2/fb-rx2/fb-rx1-rx1


sysParams.jesdLoopbackEn = 0 #Make it 1 to Enable the JESDTX to JESDRX internal loopback
sysParams.LMFSHdRx=['44210', '44210', '44210', '44210'] #44210 
# The 2nd and 4th are valid only for jesdSystemMode values in (2,6,7,8). For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb = ["22210","22210"]

sysParams.LMFSHdTx = ["44210","44210","44210","44210"]

sysParams.jesdTxProtocol = [2,2] #64b/66b
sysParams.jesdRxProtocol = [2,2] #64b/66b
sysParams.serdesFirmware = True # If you want to lead any firmware, please speify the path here. Otherwise it will not write any firmware
sysParams.jesdTxLaneMux = [0,1,2,3,4,5,6,7] 
# Enter which lanes you want in each location. 
# Note that across 2T Mux is not possible in 0.5.
# For example, if you want to exchange the first two lines of each 2T, this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxLaneMux = [0,1,2,3,4,5,6,7] 
# Enter which lanes you want in each location.
# Note that across 2R Mux is not possible in 0.5.
# For example, if you want to exchange the first two lines of each 2R, this should be [[1,0,2,3],[5,4,6,7]]

sysParams.jesdRxRbd = [4, 4]
sysParams.jesdTxRbd = [4, 4]
# scrambler is disabled
sysParams.rxJesdTxScr = [False]*4
sysParams.fbJesdTxScr = [False]*2
sysParams.jesdRxScr = [False]*4




sysParams.rxJesdTxK = [1,1,1,1]
sysParams.fbJesdTxK = [1,1]
sysParams.jesdRxK = [1,1,1,1]

sysParams.ncoFreqMode = "1KHz"

sysParams.txNco0 = [[5000,5000], #Band0, Band1 for TxA for NCO0
[6000,6000], #Band0, Band1 for TxB for NCO0
[7000,7000], #Band0, Band1 for TxC for NCO0
[8000,8000]] #Band0, Band1 for TxD for NCO0

sysParams.rxNco0 = [[3500,3500], #Band0, Band1 for RxA for NCO0
[3500,3500], #Band0, Band1 for RxB for NCO0
[3500,3500], #Band0, Band1 for RxC for NCO0
[3500,3500]] #Band0, Band1 for RxD for NCO0
sysParams.fbNco0 = [500,1800] #FBA, FBC for NCO0

sysParams.numBandsRx = [0]*4 # 0 for single, 1 for dual
sysParams.numBandsFb = [0,0] 
sysParams.numBandsTx = [0,0,0,0]

sysParams.ddcFactorRx = [4]*4 # DDC decimation factor for RX A, B, C and D
sysParams.ddcFactorFb = [4]*2
sysParams.ducFactorTx = [12]*4

AFE.systemStatus.loadTrims =1

## The following parameters sets up the LMK04828 clocking schemes
lmkParams.pllEn = True#False
lmkParams.inputClk = 1474.56#737.28
lmkParams.lmkFrefClk = True

## The following parameters sets up the register and macro dumps
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat = 0x00
logDumpInst.rewriteFile = 1
logDumpInst.rewriteFileFormat4 = 1
device.optimizeWrites = 0
device.rawWriteLogEn = 1

## The following parameters sets up the SYNCIN and SYNCOUT to interface with the TSW14J57
sysParams.jesdABLvdsSync = 1
sysParams.jesdCDLvdsSync = 1
sysParams.rxJesdTxSyncMux = [0,0,0,0]
sysParams.fbJesdTxSyncMux = [0,0]
sysParams.jesdRxSyncMux = [0,0,0,0] #[0,0,1,1]
sysParams.syncLoopBack = True


# ## The following parameters sets up the AGC
# sysParams.agcParams[0].agcMode = 1 ##internal AGC
# sysParams.agcParams[0].gpioRstEnable = 0 ##disable GPIO based reset to AGC detector 
# sysParams.agcParams[0].atken = [0, 1, 0] ##enable big and small step attack
# sysParams.agcParams[0].decayen = [0,1,0] ##enable big and small step decay
# sysParams.agcParams[0].atksize = [2,1,0] ## bigs step = 2dB, small step = 1dB
# sysParams.agcParams[0].decaysize = [2,1,0] ##big step = 2dB, small step = 1dB
# sysParams.agcParams[0].atkthreshold = [-1, -2, -14] ##attack threshold
# sysParams.agcParams[0].decaythreshold = [-14, -6, -20] ##decay threshold
# sysParams.agcParams[0].atkwinlength = [170, 170] ## detector time constant expressed inn absolute time in ns. 
# sysParams.agcParams[0].decaywinlength = 87380 ##detector time constant expressed in absolute time in ns. All detectors use the same value for decay time constant
# sysParams.agcParams[0].atkNumHitsAbs = [8,8] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock
# sysParams.agcParams[0].decayNumHitsAbs = [100,100] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock
# sysParams.agcParams[0].minDsaAttn = 0 ##minimum DSA attenuation used by AGC
# sysParams.agcParams[0].maxDsaAttn = 22 ##maximum DSA attenuation used by AGC
# sysParams.agcParams[0].totalGainRange = 22 ##total gain range used by ALC for gain compensation
# sysParams.agcParams[0].minAttnAlc = 0 ##minimum attenuation used by ALC for compensation when useMinAttnAgc = 0
# sysParams.agcParams[0].useMinAttnAgc = 1 ##enable ALC to use minimum attenuation from AGC for which compensation is required.
# sysParams.agcParams[0].alcEn = 1
# sysParams.agcParams[0].alcMode = 0 ##floating point DGC
# sysParams.agcParams[0].fltPtMode = 0 ##if exponent > 0, dont send MSB
# sysParams.agcParams[0].fltPtFmt = 1 ##3 bit exponent


## The following parameters sets up the GPIOs
sysParams.gpioMapping={
'H8': 'ADC_SYNC0',
'H7': 'ADC_SYNC1',
'N8': 'ADC_SYNC2',
'N7': 'ADC_SYNC3',
'H9': 'DAC_SYNC0',
'G9': 'DAC_SYNC1',
'N9': 'DAC_SYNC2',
'P9': 'DAC_SYNC3',
'P14': 'GLOBAL_PDN',
'K14': 'FBABTDD',
'R6': 'FBCDTDD',
'H15': ['TXATDD','TXBTDD'],
'V5': ['TXCTDD','TXDTDD'],
'E7': ['RXATDD','RXBTDD'],
'R15': ['RXCTDD','RXDTDD']}
#AFE.systemParams.papParams[0]['enable'] = True
#AFE.systemParams.papParams[1]['enable'] = True
#AFE.systemParams.papParams[2]['enable'] = True
#AFE.systemParams.papParams[3]['enable'] = True

## Initiates LMK04828 and AFE79xx Bring-up
setupParams.skipLmk = False
AFE.initializeConfig()
lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq
AFE.LMK.lmkConfig()

Could you kindly go through these scripts and tell us if there is any issue with them for our particular case( 64/66B encoding, Line Rate 12.165 Gbps) and if they could have anything do with the qpll not getting locked in chip scope.

Hi,

Between the good and the bad state do you see any difference in the EVM power consumption?

The QPLL0 locked signal comes from the Xilinx transceiver and indicates that the transceiver PLL is locked to the incoming clock. If this signal is not being set properly then this points to an issue with the clock to the transceiver quads. 

Do you have an oscilloscope that can be used to probe FPGA clock output of the LMK?

Regards,

David Chaparro 

Hi David, 

The is no notable power difference between the good and bad states. At C275 with 1474.56MHz, both vary between -43 and -45 dBm.

We have observed that according to the reference schematic the only resistors on the output wire of the FPGA clock being generated from LMK are either zero resistors or 'DNI' at R353 or R357. Hence, where exactly do we probe the FPGA clock?

Additionally, as you mentioned, the QPLL0 locked signal comes from the Xilinx transceiver and indicated that the transceiver PLL is locked to the incoming clock. If this signal is not being set properly then this indeed points to an issue with the clock to the transceiver quads. Could you suggest any rectification we make to ensure it is properly set? The oscilloscope we are using to probe the clocks is suitable up to 3.5 GHz. This should be sufficient right?

Could you kindly go through our scripts as well and confirm if they are correct given our specifications?

Hi,

To probe the FPGA transceiver clock, GTXCLK, you can probe at the C273 and/or C275. Yes, your scope is sufficient to probe the clock, 184.32MHz. 

Can you confirm that inside the Xilinx Transceiver wizard the expected clock frequency was set to 184.32MHz?

Regards,

David Chaparro 

Hi David,

We have already probed both C273 and C275 and have obtained a clock of 1474.56 MHz in both cases on either sides of the capacitor. Could you kindly confirm it?

We would like to further confirm that the expected clock frequency in the Xilinx Transceiver wizard was set to 184.32 MHz. We are sharing all the Transceiver wizard settings with you below:

Hi David,

We are using the AFE79xx LATTE GUI only to configure the LMK following the procedure given in the TI204C setup file and have assessed the board in multiple power cycles. The situation remains such that there are cases where the qpll locks immediately, but in the next power cycle it doesn't lock or it takes too long to lock sometimes even fluctuating between a locked and unlocked state. In the cases where it locks, RX and TX are working well, but in the same power on after testing for a while the qpll suddenly unlocks again.

We had initially set the REFCLOCK source for bank 129 to use the clock from bank 130 only and observed the same behaviour. Could you kindly check our LMK script to ensure that it is not issues with the script causing possible discrepancy with the register writes resulting in incorrect clock coming and could you confirm which values should be written to what register addresses so we can crosscheck with our log.

Hi, David

We want to confirm that there is no appreciable difference in the EVM current draw between the two states and we were unable to see any damage on either the board or the FMC connector. We ensured the FMC connector was pressed fully to ensure the best connection, and even tested it by changing the FMC port. However, we observed no change in the behaviour of the qpll which continues to vary with power cycles.

We would also appreciate any suggestions from your side regarding any alternative methods or material we can look into to solve this issue and move forward with our project.