IWRL6432: How to set the PMIC_CLK frequency and other options?

Tool/software:

Hello there,

The TRM says DCDC_CTRL_REG3 Offset = 1C10h permits setting the min and max frequency thresholds.

How do the values programmed into 23-16 dcdc_max_freq_thr and 7-0 dcdc_min_freq_thr of DCDC_CTRL_REG3 relate to frequency of the PMIC_CLK signal?

Also what is dcdc_freq_acc_mode in DCDC_CTRL_REG2 Offset = 1C0Ch?

Is dcdc_dither_en set to 1 in DCDC_CTRL_REG2 to permit dithering the output clock?

How does dcdc_slope_val work in DCDC_SLOPE_REG Offset = 1C14h?

These registers are listed in the TRM, but there is no advice on how to use them, and this part family has different registers than other part families.

Does one have to reset the clock somehow with 0 dcdc_rstn_reg in DCDC_CTRL_REG1 besides just enabling it?

Finally, has the L SDK added support for this stuff yet?

Thanks,

Tom.