OPT3101: Initialization

Hi Kirby,

We do not have a specific monoshot document. Have you used the configurator tool to generate the monoshot mode configuration you are using? Have you set the device to trigger from the register or from the pin?

Best,

Alex

Yes triggering from monoshot bit.  I noticed that this bit needs to be set the TG enabled then I see the data ready signal on GPIO1.  How to perform another measurement is eluding me in addition to the monoshot bit never clearing.

Here is configurator output I coded against.

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#include "OPT3101device.h"

/* OPT3101 device initialization Sequence Header file written by OPT3101 Calibration tool - Version 0.9.1
By: kirby.dotson
On: 2019-10-14 20:10:10
Configuration Settings:
{
"TXDCCurrent": 0,
"LEDOrder": 131586,
"superHDRMode": false,
"genDeviceEEPROMConnection": false,
"genDeviceI2CMasterConnection": 0,
"autoHDRMode": false,
"toolVersion": 0.9.1,
"multiLEDMode": true,
"monoshotMode": true,
"genDeviceAmbientSupport": 0,
"TX0HCurrent": 0,
"monoshotModePowerupDelay": 153,
"crc": 1304774340,
"user": kirby.dotson,
"genDeviceAvgFrameCount": 0,
"timeStamp": 2019-10-14 20:09:55,
"freqComp": false,
"monoshotModeDeepSleep": false,
"monoshotModeNFramesPerShot": 1,
}
*/
void OPT3101::device::initialize(void){
// List of registers to initialize OPT3101 device after power-up

this->reg.force_en_slave = 1; // //Since I2C Master bus is floating this register needs to be set to enable device to respond

this->reg.tg_ovl_window_start = 7000; // //Overload flab observation window
this->reg.en_temp_conv = 1; // //Enables the internal

this->reg.clip_mode_fc = 1; // //Enables Clip mode for Frequency correction
this->reg.clip_mode_temp = 0; // //Disables Clip mode for Temp coff phase correction
this->reg.clip_mode_offset = 0; // //Disables Clip mode for phase offset correction
this->reg.iq_read_data_sel = 3; // //Enables 16 bit frame counter
this->reg.iamb_max_sel = 0; // //Sets maximum ambient support
this->reg.en_temp_corr = 1; // //Enables Temperature Correction
this->reg.gpio1_obuf_en=1; // //Enabled output buffer on GPIO1 pin
this->reg.gpo1_mux_sel=2; // //select dig_gpo_0 on gpio1
this->reg.dig_gpo_sel0 = 9; // //Select Data Ready on dig_gpo_0

this->reg.monoshot_mode=3; // //Sets monoshot mode
this->reg.dis_glb_pd_refsys=1; // Disables deep sleep PWRDN for blocks
//this->reg.dis_glb_pd_temp_sens=1;
//this->reg.dis_glb_pd_illum_drv=1
//this->reg.dis_glb_pd_afe=1;
//this->reg.dis_glb_pd_afe_dac=1;
this->reg.dis_glb_pd_amb_dac=1;
this->reg.dis_glb_pd_amb_adc=1;
this->reg.dis_glb_pd_osc=1;
//this->reg.dis_glb_pd_i2chost_osc=1;
this->reg.MONOSHOT_NUMFRAME=1; // //Sets number of frames to me measured per trigger
this->reg.powerup_delay=95; // //Power-up delay for every monoshot trigger

this->reg.num_sub_frames = 0; // //Sub frames count
this->reg.num_avg_sub_frames = 0; // //Average frames count
this->reg.xtalk_filt_time_const = 10; // //Crosstalk filter time constant
this->reg.tg_seq_int_start = 9850; // //Sequence Start
this->reg.tg_seq_int_end = 9858; // //Sequence End
this->reg.tg_seq_int_mask_start = 0; // //Same as AvgFrame Count
this->reg.tg_seq_int_mask_end = 0; // //Same as AvgFrame Count

this->reg.illum_dac_h_tx0 = 31; // //High Current settings [173.6mA:5.6mA X 31]
this->reg.illum_scale_h_tx0 = 0; // //Illum scale for H [173.6mA:5.6mA X 31]

this->reg.sel_hdr_mode = 1; // //Selecting H Channel by default

this->reg.tx_seq_reg = 2184; // //Setting TX Switching order
this->reg.en_tx_switch = 1 ; // //Enable TX Switching order

this->reg.tg_en = 1; // //Enables Timing Generator

this->configurationFlags_xtalkFilterTau = 10; // //This is not a register but a settings flag for the SDK
this->configurationFlags_monoshotMode = true; // //This is not a register but a settings flag for the SDK
this->configurationFlags_xtalkSettlingOneTauInMilliSeconds = 256; // //This is not a register but a settings flag for the SDK
this->configurationFlags_xtalkSettlingOneTauInDataReadyCounts = 1024; // //This is not a register but a settings flag for the SDK
this->configurationFlags_frameTimeInMilliSeconds = 1; // //This is not a register but a settings flag for the SDK
this->configurationFlags_avgFrameCountExponentOfTwo = 0; // //This is not a register but a settings flag for the SDK

}

OPT3101::device::device(void):
configurationFlags_isTXChannelActive{true,false,false},
configurationFlags_isRegisterSetActive{false,true} {}

OPT3101::calibrationC::calibrationC(void) : calibrationC(true) {
this->recordLength = 1; // //This configuration requires 1 crosstalk and other configuration record(s)
this->registerAddressListSize= 17; // //This configuration requires 17 registers [544] bits to be stored for calibration
this->EEPROM_connected = false; // //This configuration helps configure EEPROM
this->extTempSensor_connected= true; // //This configuration helps configure Ext temp sensor
this->registerAddressList[0] = 0x31; // //Address for register(s) iphase_xtalk_reg_hdr1_tx0
this->registerAddressList[1] = 0x32; // //Address for register(s) qphase_xtalk_reg_hdr1_tx0
this->registerAddressList[2] = 0x5e; // //Address for register(s) temp_coeff_xtalk_iphase_hdr1_tx0
this->registerAddressList[3] = 0x60; // //Address for register(s) temp_coeff_xtalk_qphase_hdr1_tx0
this->registerAddressList[4] = 0x51; // //Address for register(s) phase_offset_hdr1_tx0,temp_coeff_illum_hdr1_tx0
this->registerAddressList[5] = 0x48; // //Address for register(s) tmain_calib_hdr1_tx0,tillum_calib_hdr1_tx0
this->registerAddressList[6] = 0x2d; // //Address for register(s) temp_coeff_main_hdr1_tx0
this->registerAddressList[7] = 0x52; // //Address for register(s) temp_coeff_illum_hdr1_tx0
this->registerAddressList[8] = 0x2e; // //Address for register(s) illum_xtalk_reg_scale
this->registerAddressList[9] = 0x3a; // //Address for register(s) scale_temp_coeff_xtalk
this->registerAddressList[10] = 0x71; // //Address for register(s) shift_illum_phase
this->registerAddressList[11] = 0x43; // //Address for register(s) en_phase_corr,en_temp_corr,scale_phase_temp_coeff
this->registerAddressList[12] = 0xb5; // //Address for register(s) scale_amb_phase_corr_coeff
this->registerAddressList[13] = 0x0c; // //Address for register(s) amb_phase_corr_pwl_coeff0
this->registerAddressList[14] = 0xb4; // //Address for register(s) amb_phase_corr_pwl_coeff1,amb_phase_corr_pwl_coeff2,amb_phase_corr_pwl_coeff3
this->registerAddressList[15] = 0xb8; // //Address for register(s) amb_phase_corr_pwl_x0,amb_phase_corr_pwl_x1
this->registerAddressList[16] = 0xb9; // //Address for register(s) amb_phase_corr_pwl_x2

}